Next generation computing architectures including those for machine learning and AI (Artificial Intelligence) have increasing demands on bandwidth, memory capacity and energy efficiency. All of which can be improved through the increased integration density offered by advanced packaging technologies. In this talk, we will provide an overview of the different 3D integration technologies and cover their scaling and application considerations. These include technologies for direct die to die connections such as advanced solder interconnects at 20 and 10 µm pitch and hybrid bonding or Foveros Direct to support increased interconnect density to below 10 µm pitch or more than 10,000 connections/mm2. The increased interconnect density can dramatically improve the bandwidth capability and energy efficiency. We will also cover some of the considerations for 3D die stacking such as thermal hot spots and power delivery constraints and how these can be addressed through design and packaging technology combinations. Finally, we will discuss some future directions to support continued performance improvement.