3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1].

In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated.

References:

1. “Heterogenous Integration Roadmap”, 2022, https://eps.ieee.org/hir
2. “Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling”, X. Lin et al., International Electron Devices Meeting, IEDM Technical Dig., 2021
3. “Sentaurus Interconnect User Guide”, 2022, https://www.synopsys.com/silicon/tcad
4. “Quantum ATK: An integrated platform of electronic and atomic-scale modelling tools”, S. Smidstrup et al., J. Phys.: Condens. Matter 32, 015901, 2020