SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO₂ /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations.

Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO₂/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO₂/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850^oC in H₂ to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850^oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH₂Cl₂-GeH₄-HCl gas mixture at 750^oC. Finally, the top SiO₂ is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations.

Fig. 1 shows the AFM image for surface morphology of lateral-selective Si_0.6Ge_0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO₂ and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850^oC, Si pillar/SiO₂ interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO₂/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010].

This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices.

References

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3. V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008).
4. Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014).