As semiconductor device scaling advances to sub-10 nm, leakage current and thermal consumption in the FinFET architecture will contribute greatly to device performance degradation. The Gate-all-around (GAA) structure is considered to be one of the alternatives for performance boosting. The cavity etching process for GAA structure, where sacrificial SiGe layers are selectively removed as shown in Figure 1(a), is extremely important for the later inner spacer process. The etching selectivity refers to the difference in the etching rate between two different materials. A high-quality etching recipe in this process relies on a high SiGe to Si selectivity. In our work, the design of experiment (DoE) method is applied to search for high SiGe to Si selectivity condition in the plasma-based dry etching approach: 1) the key parameters impacting the selectivity is discussed: chamber pressure, CF4 gas, O2 gas, He gas and resonant frequency (RF) power; 2) uniform design - based DoE is applied to the key parameters to generate 15 experiments on the SiGe and Si wafers; 3) the impact of the 5 key parameters on selectivity is studied as in Figure 1(b). The optimal selectivity and choice of key parameters are thus determined for the cavity etching process.