Silicon diodes, FETs, IGBTs still keep the majority of power device market, being much cheaper compared to SiC and GaN wide band gap-based devices. To keep the Si devices competitive, their manufacturing processes must be significantly improved. This includes forming Ohmic contacts. Currently the common process is PVD – physical vapor deposition of metal stacks. This process is not efficient: not selective and wasteful - metal sputtered or evaporated from target coats entire vacuum chamber, not just wafer being processed.

Electroless deposition can be potentially used for metallization of Si power devices. The electroless process can be designed selective, so the metal deposits only on silicon surface, not on areas protected by dielectric films. The deposited layer must have good adhesion to silicon surface, make Ohmic contact, and preferably converts into silicide upon anneal. Nickel satisfies all these requirements, thus is a good candidate. A major issue in Nickel plating on Si is that it does not deposits well onto very smooth polished surface of Si. Several approaches are known how to overcome this issue. Dubin [1] suggested adding pretreatment with Palladium. The Pd reacts autocatalytically on silicon surface forming Pd islands. Upon switching to Ni bath, Ni deposits on Pd first, then forms a continuous film when the islands merge.

One issue in the Pd/Ni process are that the native oxide on silicon must be removed so Pd can reach Si. In Dubin’ process this is resolved by adding HF to Pd bath. Another issue is bad process repeatability – a consequence of autocatalytic nature of the Pd plating reaction. The autocatalytic processes have uncontrollable “incubation” time, therefore repeating Pd plating with same recipe (same time) does not produce the same results.

We describe a new approach as to plate Nickel directly on polished Silicon surface. In our process the Pd activation of Si surface is replaced by a stain etch process. The stain etch is a process where crystalline Silicon is converted into porous Si layer [2]. Technically the stain etch is simply processing in a wet bath – mixture of concentrated nitric and hydrofluoric acids in a ratio around 1:1000. Same as in the Pd/Ni case, the process must be designed to exclude native Si oxide. We achieve this by direct switching from the stain bath to Ni bath, no water rinsing in between. The surface of wafer retrieved from the stain bath is highly hydrophobic (hydrogen terminated) thus there is no liquid drops on surface. A brief nitrogen gun drying is still performed, thus preventing contamination of Ni bath with HF. The hydrogen termination protects the surface. We tried both traditional Ni plating recipes – alkaline, and acidic [3], and found that Ni plating is good in both cases.

However, the resulting Ni layer is heavily non-uniform in thickness. We observe that the Ni pattern repeats the visual pattern after the stain etch. A byproduct of the stain etch reaction is hydrogen. The hydrogen forms bubbles that stick to Si surface and cause local masking, eventually non-uniformity. Thus, the key to Ni plating uniformity is the uniform stain etch. Known approaches [2] - adding surfactants to the bath, etc. happen to be only partially efficient. Therefore, we tried new stain etch recipe: add glacial acetic acid thus getting HNA mixture 1000:1:1000. The hydrogen bubbles in the old recipe were about 2 mm in diameter and kept on Si surface for many seconds. In our recipe, the bubbles get released from Si surface as soon as they reach about 0.1 mm size. The eventual Si porous layer shows uniform color appearance across entire wafers.

Notice, etching in the nitric/hydrofluoric mixture is also autocatalytic process, thus the topic of repeatability arises too. However, we use Si surface color change as the signal to finish the stain etch. Thus, we can get the same thickness porous film every time despite the incubation time varies uncontrollably.

Direct Ni plating onto blanket polished Silicon wafers with the HNA 1000:1:1000 pretreatment shows uniform mirror like appearance. Very high surface area of the porous Si enables the Ni plating. Nano scale sizes of porous Si with plated Ni result in uniform silicide upon anneal.

References

1. Dubin, V.M., "Selective electroless Ni deposition onto Pd-activated Si for integrated circuit fabrication" Thin Solid Films 226,no.1(1993):94-98.
2. Kolasinski, K.W. "Porous Si formation by galvanic etching." Handbook of Porous Silicon2 (2014).
3. Delaunois, F. Electroless nickel plating: fundamentals to applications. CRC Press, 2019.