The need of miniaturization following Moore’s law has intensified research efforts on silicon nanostructures such as nanowires or nanoribbons that can be used as active part of electronic nano-devices. In this way, nanowires offer great potential as field effect transistors channel region for ultra large scale integration electronics, and also as sensitive units for the detection of charged biochemical species for sensors on CMOS platforms. Top-down approach favors patterning architectures in a planar layout, most of the SiNWs are patterned on high cost silicon-on-insulator substrates (SOI). Polycrystalline silicon SiNWs (poly-SiNWs) synthesis using sidewall spacer top down method seems to be a lower cost alternative, fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. In such new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allow a better electrostatic gate control.

In our study, nanowires are elaborated using a classical fabrication method commonly used in microelectronic industry: the sidewall spacer formation technique. Assets of this technological process rest on the use of low cost lithographic tools, and the possibility to get by direct patterning numerous parallel nanowires with precise location on the substrate. We develop a low temperature (≤ 600°C) fabrication process of top-gate, bottom-gate and GAA FETs. Independent biasing of each gate allows a possible threshold voltage control of these bottom gate (BGT), top gate transistors (TGT) and GAA architecture. Electrical performances are analyzed as a function of the density of state highlighting oxide/semiconducting nanowire interfaces difference in top and bottom gate configurations. Applications for chemical and biochemical species sensing have also been investigated.