Recent advances in forming semiconductor heterojunctions within spatially confined nanoscale objects, including nanowires (NWs), show that the traditional limitations in the lattice-mismatched hetero-growth can be challenged. In various III-V semiconductor NWs, abrupt heterojunctions have been successfully demonstrated using the vapor-liquid-solid (VLS) growth for GaAs/InAs (7% mismatch) and InAs/InP (3% mismatch) heterojunctions. In group IV semiconductors, the approach is complicated not only by the 4.2% lattice mismatch between Si and Ge but also because Si and Ge both have a quite high solubility in the Au-Si catalyst. During chemical vapor deposition (CVD) based VLS growth using SiH₄ and GeH₄ (or similar gases), a supply of Si remains effectively “on” in the catalyst, and Si effectively intermixes with the arriving Ge even if the SiH₄ flow is already switched “off”. One way to address this problem is to choose a catalyst with a lower Si solubility, e.g. AlAu₂ and AgAu. Another possibility is to significantly reduce growth temperature before turning a GeH₄ source “on”. Using the latter technique, we fabricated Si-Ge heterojunction NWs with nearly ideal interface and only an 8 nm thick SiGe transition layer between straight and nearly micron-long Si and Ge NW segments and analyzed their structural and electrical properties. The observed changes in the photoluminescence and Raman spectra as function of temperature, non-linear and rectifying current-voltage characteristics, strong flicker noise and damped current oscillations with frequencies of 20-30 MHz are explained using the proposed SiGe heterojunction NW energy band diagram including the energy states associated with the NW surface (and near-surface) structural imperfections revealed by transmission electron microscopy and a mismatch in Si and Ge coefficients of thermal expansion.