In this presentation, we first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, channel mobility, sub-fin isolation, and sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost, Rexternal reduction) such as fin smoothing, epi Source Drain proximity or contact resistance reduction. Regarding alternate channel material, SiGe p-channel FinFET has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature and will be briefly discussed. Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to new device architecture – the Gate-All-Around (GAA) transistor - and discuss process requirements and challenges for this novel device type.