Systems integration of these devices into 3D heterogeneous System-in-Package architectures is enabling the pace of progress at the system level to maintain or exceed that of Moore’s Law. This requires new materials for conductors, dielectrics, semiconductors and interface materials. These materials will require new, lower temperature integration processes due to differential CTE and other considerations. This will also require new system architectures to support increased functional and thermal density. The interconnect fabric of these systems will dramatically change due to increasing physical density of bandwidth required that is already limiting the performance of server class computers.
There are many difficult challenges to be overcome for this HI-SiP architecture to realize its potential of maintaining that rate of progress for decades to come. These challenges and potential solutions will be discussed.