Copper (Cu) electrodeposition (ECD) in through-silicon-vias (TSVs) is an essential technique required for high-density 3-D integration of complex semiconductor devices. Cu ECD most commonly utilizes an acid sulfate electrolyte containing a finely tuned three-additive combination of inhibiting and Cu²⁺ aquo complex catalyzing species to produce void free deposits through the depth of high aspect ratio features. Despite their proven efficacy in filling micro- and nanoscale features, these three-additive electrolytes have not been shown to be viable for filling ICs at the mesoscale (> 100 µm). This is likely explained by the seminal curvature enhanced adsorbate coverage (CEAC) mechanism that describes the adsorption/desorption action of the additive species to an electrode surface. ^{[1], [2]} This mechanism theorizes that the interaction between the constituent additives and the rate of Cu²⁺ reduction is highly dependent on the local curvature of the electrode surface. In addition, these systems often require finely tuned ECD techniques like the use of pulse plating regimes, tightly controlled additive concentrations, and relatively low applied current densities (< 10 mA/cm²).

To overcome the deficiencies of the three-additive acid sulfate chemistry that the CEAC mechanism describes, a single-additive chemistry was developed for the purposes of filling conformally conductive high aspect ratio features exclusively from the bottom-up by Moffat, T.P. and Josell, D. ^[3-5] This chemistry relies on a specific polyether suppressor additive, which induces voltammetric hysteresis and a positive feedback action as metal deposition disrupts Cl^--suppressor complexes at the cathode surface. The acid sulfate resistive Cu electrolyte developed by Moffat, T.P. and Josell, D. utilizes 1 M CuSO₄ + 0.5 M H₂SO₄ in addition to µM level concentrations of chloride and polyether suppressor species.^[3-5] To investigate the functionality of a novel chemistry, the work outlined herein relies on the same mechanism and utilizes the same polyether suppressor and chloride concentration ranges, but instead uses a 1.25 M CH₃SO₃H + 0.25 M H₂SO₄ electrolyte. This electrolyte exhibits a greater Cu solubility, requires a lower concentration of acid, thus increasing the Cu plating rate while still retaining the same S-NDR mechanics as developed by Moffat, T.P. and Josell.^[3-5]

Upon adoption of the above-described chemistry, several issues were explored. The importance of convection on plating profiles within mesoscale (600 μm depth, 5:1 aspect ratio) blind TSVs is examined. In addition, potentiostatic methods are used to explore the process window for achieving bottom-up feature filling in the mesoscale TSVs described above. However, these potentiostatic techniques rely on the use of a reference electrode in solution, which is not a viable setup in industrial wafer-scale production tools. Thus, a galvanostatic approach is outlined and shown to be a viable alternative based on resulting fill profiles. The values used for the current density were calculated by comparing the breakdown potential of the suppressor molecule with the current reading at that set potential. Using only the area of the feature bottoms, a current density was calculated and fixed during subsequent plating experiments. This method is potentially problematic as the non -referenced electrochemical potential will maintain some unknown hysteresis, but initial results are shown to be promising. This galvanostatic approach, using the novel single additive chemistry is currently being explored for subsequent implementation into full wafer plating apparatus.

Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525.

1. Andricacos, P.C., et al., Damascene copper electroplating for chip interconnections. Ibm Journal of Research and Development, 1998. 42(5): p. 567-574.
2. Moffat, T.P., et al., Superconformal film growth: Mechanism and quantification. Ibm Journal of Research and Development, 2005. 49(1): p. 19-36.
3. Moffat, T. P., and D. Josell. "Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns." Journal of The Electrochemical Society 159.4 (2012): D208-D216.
4. Josell, D., D. Wheeler, and T. P. Moffat. "Modeling extreme bottom-up filling of through silicon vias." Journal of The Electrochemical Society 159.10 (2012): D570-D576.
5. Wheeler, Daniel, Thomas P. Moffat, and Daniel Josell. "Spatial-temporal modeling of extreme bottom-up filling of through-silicon-vias." Journal of The Electrochemical Society 160.12 (2013): D3260-D3265.