There is a growing interest in the integration of RF/mm wave [3] and photonic [4] components onto a large area silicon platform, to save on the overall use of III-V materials and also to allow more compact system integration. Considering the case of RF and mm wave devices in a MOSFET implementation, there is a need to understand and control electrically active defects at the interface between the III-V channel and the insulating gate oxide. In recent years there has been considerable progress in reducing the interface state density (D_it) [5-8], in narrow gap InGaAs and InGaSb [9] MOS structures to the point where genuine surface inversion can be observed for both n- and p-type InGaAs [8,9].

The research focus for III-V MOS systems is now turning to the issue of defects states in the oxide (border traps) which can communicate with the conduction and valence bands by elastic or inelastic tunnelling [10]. Analysis of these border traps to date has been based on a distributed capacitor/resistor model [10, 11]. In this presentation, we extend these studies by simulating the AC response of border traps (BTs) and interface states by employing a simulator [12, 13] that solves the Poisson, drift-diffusion and charge conservation equations, taking into account the elastic band-to-trap tunneling model [14] for BTs, yielding estimates for the trap volume as well as variation in border trap density with energy and depth into the oxide.

The presentation will also provide an overview of the relationship between specific functions of the capacitance (C) conductance (G) for the case of narrow band gap III-V MOS structures which exhibit genuine surface inversion, where the capacitance and conductance of the MOS system as a function of ac angular frequency (ω) are related, and in particular the peak values of G/ω and −dC/dlog_e(ω) (≡− ωdC/dω) are equal, and that these equal peak magnitudes occur at the same value of ω [15]. The relationship is also confirmed by physics based ac simulations of MOS structures and through analysis of the equivalent circuit model in inversion. Results will be presented for InGaAs and InGaSb MOS structures (Al₂O₃ and Al₂O₃/HfO₂ ALD oxides) where genuine inversion of the III-V/oxide surface is confirmed by the G/ω and −dC/dlog_e(ω) functions, which have peak values of C_ox²/2(C_ox+C_d) when the surface is inverted (where C_ox is the gate oxide capacitance and C_d is the maximum capacitance of the semiconductor surface in inversion). Extending on previous studies [15], this presentation will presents experimental and physics based simulations which indicate the relationship between G/ω and −dC/dlog_e(ω) holds true in all bias regions of the MOS response. Finally, it is noted that the relation between G/ω and −dC/dlog_e(ω) is not specific to III-V MOS systems, and is generally true for all MOS systems, and examples will be provides for MOS structures based on a 2 D dimensional semiconductor.

All authors acknowledge the financial support of the EU through the INSIGHT project (688784). The authors from Tyndall acknowledge Science Foundation Ireland (15/IA/3131).

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