(Invited) Dielectrics for Graphene Transistors for Emerging Integrated Circuits

In this paper, we present the use of high-k dielectric material in design and physical modeling of following two types of transistors for emerging integrated circuits: graphene nano ribbon (GNR) tunnel field-effect transistors (TFETs) and graphene short channel FETs.

Graphene nanoribbon field effect transistor (GNR FET) is one of the promising devices for emerging integrated circuits because of its exceptional electronic properties such as the large carrier mobility and planar structure. However, the problem is a high drain-source leakage current in standby state due to small band gap of graphene and short channel effect (SCE) enforced by the transistor feature size. We have proposed a new GNR FET structure which has two side gates with a lower work function than the main gate on top of the SiO₂ and HfO₂ insulating layers. The main gate and two side gates have work functions of Φ₁=4.8eV and Φ₂=4.5eV, respectively. The GNR FET width and length has been chosen 1.5nm and 15nm, where the source and drain regions are doped with a molar fraction of ionized donors equal to 5×10^-3/cm³. The lengths of the main and side gates are 2.5nm and 1.25nm while those of insulator layers have been used as a variable. We have simulated the proposed GNR FET using the self-consistent solution of three-dimensional Poisson–Schrödinger equation, within the Non-equilibrium Green’s function (NEGF) formalism. 

In our new GNR FET structure, the two side gates induce the inversion layers next to drain and source regions, which increase the controllability of the main gate on the channel potential barrier by providing an effective screen for the main gate to prevent the change in drain current due to the change in drain voltage. We have found that the application of the HfO₂ in combination of SiO₂ in the proposed GNR FET not only shifts the drain source leakage current to the lower values by several orders of magnitude but also make the leakage current sensitive to the proportionality of thicknesses of SiO₂ and HfO₂. The proposed GNR FET introduce a minimum peak in the drain source leakage current much below that of a common GNR FET with the same insulator structure. The minimum leakage currents of the proposed structure for total insulator thickness of 10Å, 15 Å and 20Å are approximately 6×10^-13A, 4×10^-12A and 5×10^-11A, respectively while those of a common GNR FET are 1.5×10^-10A, 9×10^-10A and 5×10^-9A, respectively. The minimum peak in leakage current has been obtained for HfO₂ thickness = 8Å and 14 Å corresponding to the total insulator thickness of 10 Å and 15 Å, respectively, while it shifts to purely HfO₂ insulator layer for that of 20 Å. The proposed GNR FET can diminish the short channel effect and prevent an undesirable increase in the leakage current by decreasing the channel length. 

Effect of dielectric on performance of GNR TFETs is also studied through an analytical current transport model which we have developed for designing of integrated circuits. It is observed that choice of dielectric material and corresponding thickness along the lateral gate position severely modifies performance of GNR TFET. We have found that for constant oxide thickness of 0.76nm, threshold voltage reduces from 0.176V to 0.054V for dielectric permittivity of 2.5 to 47.5. We have also noticed that the performance of GNR TFET studied through threshold voltage and sub-threshold slope depends on selection of both dielectric material and their thickness. Specific results on influence of choice of dielectric in designing of GNR TFET will be presented included in the paper and presentation.