Study of HKMG Stack Interface Engineer Applicable to 22nm/16nm Finfet Mosfet

Since Intel announced that they had made a great breakthrough in 22nm node^[1][2]on May 4, 2011, FinFET Transistor structures had almost controlled CMOS technology beyond 22nm node. In this node, with the  development of lithography, silicide process was switched to the back end. This huge change bring benefit to the formation of  HKMG stack interface engineer. Before the silicide step switched, limited by the already formed silicide, the growth temperature of interfacial oxide layer  couldn’t be higher  than 600°C for NiSi unstability at high temperature, but now 800°C or 850°C will also be allowed. So we could  adopt  thermal oxide as                HKMG stack interface layer.  

In this paper, as interface layer of HKMG stack, chemical and thermal oxide were all studied. In 32nm/22nm node Bulk Planar CMOS   technology, chemical oxide was grown through spraying DI water diluted Ozone on bare silicon substrate which was generally used in industry. It’s advantage was low thermal budget and the disadvantage was thermal unstability of Chemical ox during ALD HfOX growth. ChemOX would diffuse into HK dielectric, referred to Fig 1(b). It could also be observed very clearly at Si/ChemOX/RTCVD SIN structure , referred to Fig 2(b).  From Fig 1(a) and Fig 2(a) , we had no doubt about the stability of thermal oxide interface layer. In this article, We chose  three different thermal oxidation methods which were RTO, ISSG alone,  ISSG with plasma nitridation^[3][4]respectively.  Considering the state of silicon substrate surface  would severely affect the quality of ultrathin interface oxide layer, we also chose two different cleaning process which were HF 100:1 and BOE 100:1 last.

In conclusion, in order to improve  HKMG stack  characteristic in FinFET Transistor structures, different interface layer and cleaning  process  had been studied.  Considering the thermal unstability of  Chemical oxidation method currently used in industry, we plan to  take high quality thermal ultrathin interface oxide into 22nm node and beyond.

 References

 

[1] “Intel Reinvents Transistors Using New 3-D Structure”, http://ewsroom.intel.com/community /intel_newsroom/blog.

[2] “Roadmap for 22 nm and beyond” , H.Iwai, Volume 86, Issues 7–9, Microelectronic Engineering, 2009 .

[3] “Ultrathin DPN STI SiON liner for 40 nm low-power CMOS technology”  Chan-Yuan Hu etc.  Volume 54, Issue 5, Solid-State Electronics 2010 .

[4]“Plasma nitridation optimization of sub-15Å  gate dielectrics”  F.N. CUBAYNES etc.   International Symposium on Silicon Nitride and Silicon Dioxide Thin Insulating Films, 28 April - 2 May 2003, Paris, France.