Requirements and Difficult Challenges for Packaging in the Era of “More Than Moore”

The benefits of Moore’s Law are slowing as we reach the limits of scaling imposed by the laws of physics. The advantages of higher speed and lower power requirements no longer scale with device feature size. One approach to increase functional density as the benefits of scaling slow is to incorporate functional diversification within a single package. Combining analog, RF, power devices, optical devices, MEMS and other devices types into a single package enables this functional diversification. System-in-package (SiP) architectures combining these components with logic and memory that follow Moore’s Law offsetting much of the decreased benefits of scaling has been called “More than Moore”.

This sounds very simple but there are many difficult challenges that arise in incorporating components with diverse requirements into a single, high density package and delivering the reliable performance demanded by the markets. These challenges include:

 

• Lack of adequate modeling and simulation tools for complex SiP packages
• Thermal management with increased thermal density, “hot spots”, etc.
• Stress and warpage associated with CTE differences between various components
• Cross talk between components
• Protecting fragile components such as thinned die, MEMS and compound semiconductors
• Maintaining power integrity with widely varying power requirements of various components
• Requirements for both hermitic and open packages for sensor environmental access

There are many other challenges as we increase the density of components and interconnect wiring, incorporate heterogeneous integration of both component types and materials used, support a wide range of supply voltages from below 400mV to several volts and incorporate 3D integration. Perhaps the most difficult challenge is to meet these expanding requirements while continuously driving down the cost per function demanded by the markets. Traditionally, packaging has not scaled down in cost with shrinking geometries as quickly as CMOS integrated circuits. Introduction of complex “More than Moore” SiP packages makes this cost challenge much more difficult.

The ITRS was established to forecast the difficult challenges that must be met to satisfy future requirements with sufficient lead time to allow implement a solution. This process has been very successful and, since the beginning of the ITRS, packaging challenges have not prevented continued end user product cost reduction and performance increases. The packaging solutions needed now to continue these improvements in size, cost and performance cannot be delivered by continuing down a known path as we did with CMOS scaled integrated circuits.

Everything has to change.

This includes package architectures, design and simulation tools, materials, connections, etc. Many of these changes are underway but there is much more to come. Specific examples of requirements, challenges and potential solutions for packaging in the Era of ‘More than Moore” identified in the 2013 ITRS will be discussed.