PECVD and Thermal Gate Oxides on 3C vs. 4H SiC – Impact on Leakage, Traps and Energy Offsets

Silicon carbide (SiC) is particularly suitable for manufacturing of medium and high power FETs. Two SiC polytypes most commonly used for that purpose, i.e. cubic 3C and hexagonal 4H, differ, however, in many aspects, which influence the operation of the  devices. The  differences in interface trap distributions, gate leakage and energy band model offsets resulting from the SiC polytypes were investigated in this work.

Samples. Characterized were two lots of wafers (3C-SiC and 4H-SiC) fabricated by Acreo AB. The 3C-SiC lot consisted of two n-type (001) 3C-SiC wafers. The substrates from Hoya were covered at Acreo by a n-type epitaxial layer with nitrogen doping of 7×10¹⁵ cm^-3. One  wafer was  thermally oxidized in wet oxygen (T = 1150°C, 1h) while the other had the SiO₂ layer deposited by PECVD at T = 300°C. This second wafer was further annealed for 3 hours in wet oxygen at T = 950°C. The oxide thickness on both wafers was 60 nm.

The 4H-SiC lot consisted of two SiC-4H n-type wafers, one with a thermal (53 nm) and another with a PECVD (45 nm) gate oxide fabricated in the processes analogical to the 3C-SiC lot.

Measurements.The gate leakage currents were measured on Agilent B1500AB. The interface trap distributions were measured by standard conductance method on Agilent 4294A. The energy band model offsets were established  using our own specialized equipment for photoelectric measurements. The methods used were discussed in details in [1,2,3].

Results. The important difference between the 3C and 4H polytypes is the width of the energy gap:  E_G(3C)=2.36 eV and E_G(4H)=3.23 eV [4]. In Fig. 1 the trap density distributions measured in the samples in both polytypes are presented. The energy axis shows the trap distance from the top of the valence band E_V, what enables the comparison of  D_it in both systems. As  expected, the D_it values in 4H-SiC are higher than those in 3C-SiC, irrespective of the oxide preparation method, due to the presence of a band of interface traps in the oxide, so called NIT (near-interface traps), caused probably by oxygen vacancy defects (O₃ΞSiH HSiΞO₃)  producing trapping states at 3.0 eV...3.2 eV above E_V, as reported by Afanas’ev [4] and others [5].

An interesting feature can be demonstrated comparing  gate leakage currents. In Fig. 2 we present the averaged leakage current density characteristics measured in both polytype samples. One can notice a very small difference in the leakage current density J between the oxides, while the difference with respect to the substrate polytype is very large. The density of leakage currents in 4H is by two orders of magnitude lower than that in 3C. Since the oxide preparation procedure in both samples was identical, the difference could not be explained by the oxide properties only. We presume that the mechanism of the increased leakage in the 3C-SiC is connected with trap enhanced tunneling from the conductance band by the NIT defects.

Finally we present the most important 3C- and 4H-SiC MOSC energy-band model offsets shown in Fig. 3. The offset values are given in Tab. 1. All the values were taken for PECVD oxide and Al gate.

Conclusions

Energy-band model offsets, trap density distributions and gate leakage characteristics of MOS capacitors with PECVD and thermal gate oxide on 3C- and 4H-SiC were compared. The important role of NIT traps in both polytypes influencing different device characteristics was demonstrated.

References

1.H.M.Przewlocki, Solid State Electron. 45 (2001),1241.

2.V.V.Afanas’ev, Internal Photoemission, Elsevier,2008.

3.K.Piskorski et al, Opto-Electron. Rev. 20, 67, 2012.

4. V.V.Afanas’ev, Microel. Eng. 448 (1999), 241-248.

5. M.Krieger et al., Mat.Sci.Forum 645-648 (2010), 463-468.