Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains

Very low temperatures (i.e. 500°C and below) are highly desirable for the fabrication of SiGe:B Raised Sources and Drains (RSDs) in advanced MOSFETs (notably if they are stacked one upon another thanks a sequential integration scheme). We have thus leveraged our know-how on (i) disilane-based epitaxial growth (Thin Solid Films 520, 3185 (2012); Thin Solid Films 557, 19 (2014)) and (ii) Cyclic Deposition / Etch (*) strategies (Semicond. Sci. Techno. 28, 025017 and 025018 (2013)) to develop an innovative 500°C process for the selective deposition of heavily in-situboron-doped SiGe:B RSDs.

We have first of all evaluated the impact of diborane on the 500°C, 20 Torr growth kinetics of SiGe:B. The growth rate significantly increased while the Ge content decreased as B₂H₆ was added to disilane + germane:  from 3 up to 14 nm min.^-1 and from 45% down to 28%, respectively. Layers were of excellent crystalline quality even for high substitutional B concentrations (from strain compensation: at most 5x10²⁰ cm^-3). The resistivity achieved, ~4x10^-4 Ohm.cm, was a factor of two lower than our usual 650°C process. We have then studied whether or not straightforward SiGe:B Selective Epitaxial Growth (SEG) was feasible by adding HCl, an etchant gas that promotes selectivity on patterned wafers, to the gaseous mixture. As expected, the SiGe:B growth rate decreased while the Ge content increased with the HCl flow. The poly-SiGe:B growth rate on SiO₂-covered Si wafers was close to the single-crystalline growth rate on blanket Si wafers, however (even for high HCl flows). Simple SEG thus does not seem to be feasible at 500°C with Si₂H₆ + GeH₄.

We have thus benchmarked various CDE strategies in order to obtain the selectivity aimed for at 500°C. The overall deposition time was constant at 432s, while various HCl partial pressures and total etch pressures were tested in either simple Deposition / Etch processes or 12 cycles CDE processes. For cyclic processes, low HCl flows and etch pressures (20 Torr) resulted in almost nil poly-SiGeB etch rates (0.4 nm min.^-1 only). Significantly increasing both the HCl flow and the total etch pressure (80 Torr) delivered the poly-SiGe:B etch rates sought after (4 nm min.^-1). The etch selectivity (i.e. the poly-SiGe:B etch rate on SiO₂-covered substrates divided by the SiGe:B etch rate on blanket Si) was low, however (2.7 only). The resulting SiGe:B layers were otherwise 3D for long etch durations, making such CDE processes unusable (as for chlorinated chemistries at 650°C; see Solid State Electronics 83, 10 (2013)). We have thus resorted to simpler 500°C DE process, with a single etch step at 740 Torr (atmospheric pressure) after the 20 Torr growth of the whole layer. The etch selectivity was improved when switching from high to medium HCl flows (from 2.6 up to 4.8), while still having high poly-SiGeB etch rates (24 nm min.^-1). The resulting SiGe:B layers were compressively-strained and of high crystalline quality (although the surface was roughened a bit).

We have then switched to patterned SOI wafers with gate stacks and studied the feasibility of such a DE process. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces like the SiO₂isolation or the SiN spacers; rather smooth, facetted SiGe:B raised sources and drains were obtained in the end, as illustrated in the figure.

(*) CDE consists in alternating between non selective epitaxial growth steps and selective etch steps, during which the few nm thick poly-crystalline layer deposited on dielectrics is etched much faster that the single-crystalline layer inside Si windows.