(Invited) Ge-on-Insulator MOSFETs for High-Performance and 3D-LSI Applications

Tuesday, 7 October 2014: 10:40
Expo Center, 1st Floor, Universal 17 (Moon Palace Resort)
T. Tezuka, K. Ikeda, Y. Kamata, Y. Kamimuta, K. Usuda, Y. Moriyama, M. Ono, M. Koike, M. Oda, T. Irisawa, E. Mieda, T. Maeda (National Institute of Advanced Industrial Science and Technology (AIST)), W. Jevasuwan (National Institute for Advanced Industrial Science and Technology (AIST)), Y. Kurashima, H. Takagi, K. Furuse, and E. Kurosawa (National Institute of Advanced Industrial Science and Technology (AIST))
Germanium is recognized as new channel material to be introduced in near future CMOS technologies. The advantages are the high hole mobility, the high p-type dopant activation and the low contact resistivity, whereas the smaller band gap results in higher off state current than Si devices. Therefore, Ge-MOSFETs are considered to be most promising to use as a pMOS counterpart of III-V nMOSFETs for high-performance CMOS devices. In order to suppress the off leakage current, Ge-on-insulator (GeOI) substrates may be preferable than bulk substrates. On the other hand, the low thermal budget of the fabrication processes can provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs instead of a TSV technology. Poly-Ge CMOS devices on insulating layers may be one of solutions for the 3D-LSIs. In this paper, electrical properties and processes of high performance strained Ge nanowire pMOSFETs and poly-Ge trigate pFETs both on buried oxide (SiO2) layers, which are dedicated for the former and the latter applications, respectively, are presented.

The Ge nanowire devices were formed by a two-step Ge condensation technique for the channels and a self-aligned NiGe process for the source and drain [1]. A compressive strain of around 4% along the channel direction of <110> was observed after the condensation process, suggesting that no relaxation of the misfit strain between Si and Ge was occurred. A significantly high-hole mobility of 1922 cm2/Vs has been achieved thanks to the high strain and the good interfacial quality between the gate insulator and the Ge channel. Ion/Ioff over 105 has also been attained for the Ge nanowire pMOSFET with a gate length (Lg) of 45 nm. Poly-Ge junction-less (JL) pFETs with a Lg down to 40 nm were formed on a SiO2 layer on a Si substrate [2]. The poly-Ge channel was naturally p-type with a hole concentration around 5x1018 cm-3 presumably due to the crystalline defects. No additional doping has been done. A high Ion/Ioff of around 105 was observed for narrow fin (7 nm) devices, although wider devices (>11 nm) exhibited degraded cut-off characteristics. We also found that  the current drivability was drastically improved by using a flash lamp annealing (FLA) method due to the high hole mobility in the poly-Ge channel. A drain current value of 280 μA/μm was achieved at Vd=-1 V for the Lg=80 nm device [3], which is comparable with that of a mono-crystalline Si-pMOSFET of 130-nm technology node.

In summary, two types of GeOI pMOSFETs for near-future high-performance logic CMOS-ICs and low-cost stackable applications were demonstrated. In both types of devices, the GeOI platform and non-planar gate configurations are key technologies to achieve sufficiently high Ion/Ioffvalues, which is one of major concerns to implement Ge devices into markets.


This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP).


[1] K. Ikeda et al., Symp. VLSI Tech., (2013), T30

[2] Y. Kamata et al., Symp. VLSI Tech., (2013), T94

[3] K. Usuda, ISDRS 2013 WP3-04