(Invited) The Impact of a (Si)Ge Heterojunction on the Analog Performance of Vertical Tunnel FETs
All analyzed vertical nanowire TFETs were fabricated at imec/Belgium with the following characteristics: a total channel length (LCH) of 220 nm, a physical gate length (LG) of 150 nm, a gate/drain underlap (LGD) of 100 nm, a gate/source overlap (LGS) of 30 nm and the gate dielectric is composed by 3nm HfO2 on top of 1nm interfacial SiO2. The TFETs studied here have a diameter (D) of 200 nm, with 100 nanowires in parallel (NW=100). A layer of Si1-xGex (=source) is deposited prior to the nanowire (NW) etching on top of the undoped silicon channel layer in the case of SiGe hetero-TFETs. Three different source compositions are studied: 100% Si, Si0.73Ge0.27 and Si0.56Ge0.44. For the Si source devices, 2 different devices are evaluated: the first one has the source doped by ion implantation after gate stack etching (= self aligned), while for the second device the source was like for the SiGe source counterparts in situ B-doped epitaxial grown prior to the NW etching. As a result, the second case corresponds to a more abrupt junction profile. Considering the Si0.54Ge0.46 source composition, the studied splits have 3 different Si capping process conditions after NW etching: 12 Si Mono-Layers (MLs), 18 Si MLs and the reference that has no extra Si passivation. More details can be found in (3).
The impact of the source composition on the TFET behavior can be evaluated through figure 1. By increasing the germanium amount in the source, the bandgap decreases which results in an increased BTBT and a higher on-state current (ION). However, an inversion on the off-state current (IOFF) trend was observed. When the different Si source devices (inset of fig.1) are considered, the abrupt junction device presents a higher ION, due to the higher BTBT.
Focusing on the Si0.56Ge0.44 condition that presents the best TFET behavior at room temperature, 3 different Si capping conditions were analyzed (fig.2). When Si MLs are included in the process a smaller amount of germanium segregates at the oxide, reducing the charges into the gate oxide and consequently improving the low frequency noise (inset of fig.2). At the same time, devices with Si MLs present a hump in the off region due to the increase of interface traps. This interface traps increase also promotes a shift in the drain current (IDS) to higher gate voltages.
In the output characteristics of TFET devices, there is a very flat plateau in a “like saturation” region due to the small drain voltage influence on the transport mechanism (4), showing that the TFET is a good alternative for analog applications.
Based on these characteristics, the analog parameters were extracted and analyzed as a function of temperature. Table I shows the results obtained for the Early voltage and figure 3 presents the intrinsic voltage gain behavior for temperatures ranging from 25 º C to 150 º C.
From table I it is possible to observe that in general with increasing the germanium amount in the source side, the Early Voltage (VEA) increases due to the smaller tunneling resistance near the source. However, when the VEA is evaluated at higher temperatures, it is possible to see that the higher the Ge amount in the source, the greater the VEA degradation. This degradation is a result of the dependence of the dominant transport mechanism on temperature. For Si non-abrupt source devices, the inverse trend is observed, because in this case the dominant transport mechanism is trap assisted tunneling (TAT), which is strongly influenced by a temperature increase.
Since the intrinsic voltage gain (AV) can be calculated by AV=gm/IDS*VEA=gm/gD and VEA prevails over the gm/IDS ratio, the intrinsic voltage gain behavior as a function of temperature has the same trend as VEA.
A more extensive discussion about the analog performance of TFETs with different source compositions will be presented.
1. W. Y. Choi et al., IEEE Electron Device Lett., 28, 743 (2007).
2. R. Rooyackers et al., IEDM, 92 (2013).
3. A. Vandooren et al., Solid-State Electronics, 78, 82 (2012).