Design Considerations for ZnO Transistors Made Using Spatial ALD

Monday, 6 October 2014: 15:40
Expo Center, 1st Floor, Universal 16 (Moon Palace Resort)
S. F. Nelson, C. R. Ellinger, and L. W. Tutt (Eastman Kodak Company)
We have used spatial atomic layer deposition (SALD) to fabricate a variety of thin film transistors using zinc oxide as the semiconductor and aluminum oxide as the insulator. The conductive electrodes are formed either from aluminum-doped zinc oxide, or from thermally evaporated metals.  Spatial ALD can be performed at atmospheric pressure, and can grow coatings very quickly. Deposition occurs without a requirement for valve timing, by moving the substrate relative to the precursors flowing from a coating head.  The proximity of the substrate to the coating head is controlled via a gas bearing design – allowing SALD to operate with purge times that are equivalent to the precursor exposure times (sub-second) unlike traditional chamber-based systems. 

In this talk we will discuss examples of thin film electronics with architectures that are enabled by ALD, with a particular focus on spatial ALD.  We use the well known conformality of ALD to build self-aligned, sub-micron channel length, vertical transistors. The vertical transistor electrical performance is impressive compared to amorphous silicon TFTs, for example, yet the alignment tolerances inherent in the fabrication process are large.

Our second approach to fabricating devices uses selective area deposition, with inkjet-printed inhibitor, to pattern all the active layers. We build full transistors and circuits using one inhibitor ink, the SALD system, and an oxygen plasma to clean the substrate. Performance of the resulting transistors and circuits match photolithographically patterned ones.