Design Considerations for ZnO Transistors Made Using Spatial ALD
In this talk we will discuss examples of thin film electronics with architectures that are enabled by ALD, with a particular focus on spatial ALD. We use the well known conformality of ALD to build self-aligned, sub-micron channel length, vertical transistors. The vertical transistor electrical performance is impressive compared to amorphous silicon TFTs, for example, yet the alignment tolerances inherent in the fabrication process are large.
Our second approach to fabricating devices uses selective area deposition, with inkjet-printed inhibitor, to pattern all the active layers. We build full transistors and circuits using one inhibitor ink, the SALD system, and an oxygen plasma to clean the substrate. Performance of the resulting transistors and circuits match photolithographically patterned ones.