Materials Issues in Hermetic Wafer Level Packaging Using Au Thermocompression and Au-Sn Transient Liquid Phase Bonding

The three-dimensional integration of circuits is becoming increasingly important in current and future electronics, optoelectronics, and photonics often requires a high vacuum level to properly function.  To achieve this level of vacuum without using pumping systems, the chips need to be packaged hermetically.  This can represent more than 70% of the fabrication cost when devices are packaged individually.  In this context, wafer-level packaging (WLP) has emerged a powerful paradigm to make the process of integration cost-effective.  Herein, we present recent advances in gold assisted bonding techniques to achieve a hermetic and strong bonding for large scale applications.  More specifically, we will discuss design and materials issues required to enable optimized gold thermocompression (Au TC) and gold-tin transient liquid phase (AuSn TLP) bonding of 6 and 8-inch wafers.  Moreover, we will also present in situ and ex situ investigations of the basic mechanisms governing these bonding processes.  A deep understanding of these fundamental aspects is vital to achieve a better control of WLP technologies.

Au TC bonding is obtained through two different approaches: (1) Standard flat surfaces; and (2) patterned micro-scale seal rings with grooves etched in silicon.  The bonding conditions are chosen to minimize the processing steps and cost, while obtaining a strong hermetically sealed cavity.  The first tests are made on deep reaction-ion etched pillars bonded to blanket wafers.  Both wafers are completely coated with Ti/TiN/Au (10/100/500 nm) deposited by sputtering, acting as an adhesion layer, a diffusion barrier, and the bonding interlayer, as shown in Figure 1(a).  Although the bonding withstands post manipulations, under certain conditions, cracks may develop throughout the wafers, as presented in the scanning acoustic microscopy (SAM) image of Figure 1(b).  Bonding using flat seal rings is also achieved and studied using SAM, scanning electron microscopy (SEM), and shear tests to evaluate the quality of the interface.

AuSn TLP bonding is achieved using a near eutectic electrodeposited AuSn layer pressed between two pure sputtered gold layers.  Different thicknesses are chosen to obtain a uniform Au₅Sn final phase.  These layers have to be thick enough for the interdiffusion step to be long enough to obtain a uniform interface, while being as thin as possible to reduce the material cost in the integration process.

The optimization of these two bonding processes requires the fundamental understanding of the thermal stability of the stacks considered.  Indeed, our observations show that the formation of cracks at the interface of Au TC bonded wafers is strongly related to the thermal stability of the diffusion barrier.  In order to further elucidate this phenomenon, we have undertaken prior to the wafer bonding detailed and extensive in situ and ex situ studies of the behavior of the wafers and layer stacks during thermal annealing using  photo-emission electron microscopy (PEEM, Figure 1(c)-(d)), low energy electron microscopy (LEEM), SEM, atomic force microscopy (AFM) and transmission electron microscopy (TEM).  The effect of pinholes in the TiN diffusion barrier on the composition and morphology of the Au layer is also studied The alloy phase formation and the intermixing rate of Au and AuSn are studied through thermal annealing combined with ex situ SEM and TEM, along with in situ PEEM.  The knowledge developed during these studies allowed an optimization of the layer thicknesses and the bonding recipe.