Three-Dimensional Integration of Fully Depleted Silicon-on-Insulator Transistor Substrates for CMOS Image Sensors Using Au/SiO2 Hybrid Bonding and XeF2 Etching

Wafer bonding is a promising technology to enhance the performance and functionality of integrated circuits including memory devices, and large improvements have been made also in CMOS image sensors. In previous work, direct SiO₂-SiO₂ bonding and adhesive bonding techniques were employed to develop CMOS image sensors of a back-illumination type [1,2]. For cellular phone cameras, for instance, wafer bonding of an imaging pixel substrate and a logic circuit substrate was demonstrated to considerably reduce the chip size [3]. Cu-Cu bonding was reported to bond the III-V compound infrared detector array and the CMOS readout circuit, thereby reducing power consumption [4]. Wafer bonding is also expected to overcome the limitations of the conventional CMOS image sensors, such as dynamic range and signal processing capability [5,6].

We have investigated an image sensor for future TV broadcast equipment, where pixel-parallel signal processing is needed. As shown in Fig. 1, three-dimensional (3D) device containing functional layers is made up of components such as photodiodes and signal processors through the pixel-wise vertical interconnections [7-9]. The signal from each photodiode is processed by the analog-to-digital converters within the pixel and read out in parallel. This new architecture allows a significantly large number of scanning lines than the conventional planar image sensors would do by the column-parallel signal processing architecture.

To implement the structure of the image sensor, we developed a fabrication process for 3D integration of fully depleted silicon-on-insulator (FDSOI) transistor substrates by Au/SiO₂ hybrid bonding and XeF₂ etching [2,8]. Figure 2 shows a test chip that was experimentally constructed to demonstrate the effectiveness of this approach. The chip consists of a back-illuminated photodiode layer (upper substrate) and a signal processor layer (bottom substrate).

Figure 3 illustrates the chip fabrication process. (a) FETs were first formed on FDSOI substrates. (b) Via holes were produced in the intermediate SiO₂ layer by dry etching. (c) A Ti seed layer was deposited by sputtering and a Au film was formed by electroplating. (d) A Au/SiO₂ hybrid surface was formed by chemical mechanical polishing (CMP), and the corresponding atomic force microscopy (AFM) image is shown in Fig. 4. (e) The hybrid surface was treated sequentially with Ar and O₂ plasma, and the substrates were cooled to 15 °C to promote the absorption of water molecules on their surface. (f) The substrates were directly bonded using a force of 2000 N for 60 min at 200 °C and 1 Pa (Fig. 5(a)). (g) The Si handle layer of the upper substrate was removed to allow the light transmission to the photodiode. The handle layer was first thinned to 40 µm (Fig. 5(b)). (h) The remaining Si was removed by 75 cycles of XeF₂ etching at 400 Pa for 30 s. Since the buried SiO₂ acted as a natural etch stop, a completely smooth back surface could be obtained, as shown in Fig. 5(c). Figure 6 shows a cross-sectional scanning electron microscopy (SEM) image of the fabricated chip. Following the removal of the Si handle layer, the remaining thickness of the upper substrate was 6.5 µm. The alignment error was determined to be less than 3 µm and no interfacial voids were identified. From these results, it was concluded that a 3D test chip was successfully developed using the proposed method. This process is promising to stack more than 3 layers of substrate by repetition and to form additional backside electrodes [9].

In conclusion, an experimental test chip was successfully fabricated using the Au/SiO₂ hybrid bonding and the XeF₂ etching to demonstrate the 3D integration of image sensor. The results clearly indicate the feasibility of fabrication method toward image sensors.

References

[1] V. Suntharalingam et al., IISW 2007, pp. 155-157.

[2] B. Pain et al., IISW 2007, pp. 158-161.

[3] S. Sukegawa et al., ISSCC 2013, pp. 484-486.

[4] D. S. Temple et al., LTB-3D 2012, p. 31.

[5] J. Aoki et al., ISSCC 2013, pp. 482-484.

[6] K. Kiyoyama et al., IEEE 3DIC 2011, 5-1.

[7] M. Goto et al., IEEE S3S 2013, 11.2.

[8] K. Hagiwara et al., WaferBond’13, pp. 125-126.

[9] M. Goto et al., 222^nd ECS, 2790.