An Industrial 650V GaN DHEMT Cascode Technology
Devices are processed on 6 inch GaN-on-Si wafers, using a standard CMOS production line. Passivation of the AlGaN surface is done using an in-situ SiN. The N-atoms in the SiN layer terminate the III-site dangling bonds, see Figs.1. Detailed physical and electrical characterization (CV and Cp-Gp analysis) is performed, see Figs. 2. The narrow <Gp>/ω frequency spectra, the absence of slow traps and the low extracted interface trap density point to high quality interfaces, both at the hetero-structure as well at the dielectric interface. A typical transfer and output characteristic of a 650V DHEMT with Lgd=15µm is shown in Figs. 3a and 3b respectively. Vth is around -4.5V, gate leakage is below 10 pA/mm. Ion/Ioff ratio is 3x109. At Vgs=0V, the on-state saturation current is 0.5A/mm. Fig. 4 shows the on- and off-state of a large power device (W=364mm). The measured Ron is 40mΩ (current force of 50A), while the off-state gate and drain leakage at 650V is below 2nA and 100nA respectively. Hence the in-situ SiN constitutes a very low leaky gate and good passivation of the access regions. Further characterization and results will be reported on static and switching energy power loss demonstrating the excellent performance of GaN based devices. Also current collapse is studied through PIV measurements and TDDB reliability is studied indicating lifetime above 10yr.
A normally off function is realized through cascoding the 650V DHEMT with a LV Si MOSFET. In such a system, the interactions of the internal nodes between Si FET and GaN HEMT, it’s parasitic (especially inductors), and the properties of the system will largely impact energy efficiency, ringing behavior, as well as reliability and even destruction during operation. A mixed-mode simulation methodology is developed, using calibrated TCAD decks for the active devices integrated in a Spice circuit using calibrated models for the passives, see Fig.5 for the case of a boost PFC. This allows looking into all nodes, and even into internal field and carrier distributions within the devices during operation. Waveforms, power loss breakdowns and efficiencies can be extracted. It also allows to easily generate and compareprocess or layout changes for total system optimization. Fig.6 gives the example of simulated and measured waveforms of the cascoded DHEMT rectifier in a boost PFC (Fig. 5). It is found that significant power loss during turn-on, a well as severe shoot through and other anomalies can occur when loop inductances etc. are not optimized. Additional simulation data and measurements both for a cascoded rectifier and a cascoded switch will be reported.