Advances in Diamond Integration for Thermal Management in GaN Power HEMTs

Tuesday, 7 October 2014: 11:30
Expo Center, 1st Floor, Universal 20 (Moon Palace Resort)
T. J. Anderson, K. D. Hobart, M. J. Tadjer, A. D. Koehler, T. I. Feygelson, B. B. Pate (Naval Research Laboratory), J. K. Hite (U.S. Naval Research Laboratory), F. J. Kub, and C. R. Eddy Jr. (Naval Research Laboratory)
The gallium nitride (GaN) materials system is an attractive wide-bandgap material for next-generation power devices, including RF amplifiers, high voltage power switches, and high breakdown voltage diodes. Self-heating effects, however, have limited the device capabilities. Attempts to mitigate thermal impairment have been limited due to the difficulties involved with placing high thermal conductivity materials close to heat sources in the device. Heat spreading schemes have been proposed involving growth of AlGaN/GaN on single crystal or CVD diamond, or capping of fully-processed HEMTs using nanocrystalline diamond (NCD). All approaches have suffered from reduced HEMT performance or limited substrate size.

Recently, we have successfully demonstrated a “gate after diamond” approach, which enables scalable, large-area diamond integration and improves the thermal budget of the process by depositing NCD before the thermally sensitive Schottky metal gate [1,2]. The diamond-capped device appeared to demonstrate improved DC I-V characteristics in most key performance areas, notably improved on-resistance, saturation current, and transconductance, and reduced off-state current and gate leakage, and a 20% reduction in channel temperature as measured by Raman thermography. Thermal mapping has also indicated a change in the temperature profile through the source-drain region by pulling the hot spot away from the gate edge and broadening the temperature distribution. 

This process has recently been improved to enable the deposition of diamond directly on the GaN surface by using a sacrificial layer to protect the gate region in the diamond recess etch step. As the diamond has been shown to mitigate current collapse as much as SiNx, the need for a thin passivation layer, which is an additional thermal boundary in the layer structure, has been effectively eliminated. To further address thermal limitations, a back-side diamond via process has also been developed. High aspect ratio vias are fabricated in Si substrates, followed by a conformal diamond coating.

Finaly, taking advantage of the ability to control doping in the NCD layer, we have demonstrated the use of diamond as a gate electrode. The boron-doped p-NCD is both transparent, enabling optical probing under the gate, and thermally stable, enabling operation in extreme environments and facilitating integration with other high-temperature processing steps, such as top-side and back-side undoped diamond heat spreading films. An additional advantage of this device structure is that the gate electrode is governed by the NCD-AlGaN heterojunction, which is inherently lower leakage than the conventional Schottky diode. Furthermore, if high doping levels can be achieved at the interface, the p-n junction can deplete the 2DEG, presenting a novel path to enhancement-mode devices.

This presentation will review progress in simulation, process integration, channel temperature mapping, and electrical characterization of diamond-capped devices.

1. M.J. Tadjer, T.J. Anderson, K.D. Hobart, T.I. Feygelson, J.D. Caldwell, C.R. Eddy, Jr. F.J. Kub, J.E. Butler, B.B. Pate, J. Melngailis. IEEE Electron Dev. Lett. 33, 23-25 (2012)

2. T.J. Anderson, A.D. Koehler, M.J. Tadjer, K.D. Hobart, T.I. Feygelson, J.K. Hite, B.B. Pate, C.R. Eddy, Jr, F.J. Kub. 2013 CS Mantech Technical Digest