Monolithic Thin Wafer Stacking Using Low Temperture Direct Bonding

Due to the high process temperature required for fusion bonding (e.g. ~1000°C) this process was not attractive for 3D applications. In the recent years low temperature fusion bonding processes were developed for addressing such applications: in such process the maximum temperature ranges typically between 200°C – 400°C.

A low temperature thin wafer stacking process was developed. The low temperature fusion bonding process was used in combination with standard thin wafer manufacturing processes based on temporary bonding/debonding technology in order to demonstrate thin layer direct bonding with subsequent multi-layer stacking capability.

Temporary bonding is an enabling technology to manufacture and securely handle wafers with a thickness of < 20 µm.  Thin wafer processing is enabled by temporary bonding the device wafer to a rigid carrier wafer using temporary bonding adhesives which allow subsequent thinning and backside processing of the device wafer. Two different processes for the thin wafer manufacturing and thin wafer stacking capability were evaluated. The process flow for thin wafer stacking is shown in Figure 1 and can be divided into four major tasks: thin wafer manufacturing, surface preparation, wafer bonding and carrier removal.

Experimental data of temporary bonded wafers with a wafer thickness of < 10 µm and a TTV ≤2 µm for 300 mm silicon wafers will be presented.

Low temperature oxide deposition followed by a Chemical Mechanical Polishing (CMP) process was evaluated on the thinned wafers to enable a direct bonding process and to first layer an extensive layer preparation process was performed to enable the stacking of the second layer [2].

The process is compatible with the high cleanliness levels required by CMOS technology and can be used for various application scenarios involving Through-Silicon Vias (TSV) technology.