(Invited) High Ge Content SiGe Thin Films: Growth, Properties and Integration

Thursday, 9 October 2014: 12:50
Expo Center, 1st Floor, Universal 7 (Moon Palace Resort)
A. Y. Hikavyy, E. Rosseel, S. K. Dhayalan, L. Witters, H. Mertens, H. Bender, P. Favia, and R. Loo (IMEC)
Although SiGe with low Ge content was used in BiCMOS devices for a relatively long time, its integration in pMOS transistors at 90 nm technological node opened for SiGe totally new horizons. During the course of years Ge content in SiGe gradually increased, as well as its influence. Nowadays, practically every pMOS transistor is using SiGe either as a strain booster in the case of high performance pMOS or as a SiGe channel allowing Vt correction of low power pMOS transistors. Integration of high mobility materials (SiGe, Ge) in the fin FET fashion seem to be rather logical step in order to move to the next 10 nm technological node and beyond.

In this contribution we will first discuss the growth of SiGe with high Ge content with different precursors like silane, disilane, germane and digermane (Fig. 1). 

Next we will elaborate on relaxation of SiGe thin films (plastic and elastic (Fig. 2)) and SiGe processes selectivity. 

Finally we will present the integration of high Ge content SiGe in different types of pMOS transistors: Si FinFETs, strained SiGe core FinFETs, strained SiGe cladding FETs and strained Ge FETs (Fig. 3). 

Challenges and possible solutions for different pMOS approaches listed above will be put forward.


The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.

Fig.1 Ge concentration of SiGe grown with different precursors at different temperatures.

Fig.2 An example of elastic relaxation of SiGe caused by too high process temperature.

Fig.3 Examples of SiGe integration in different device structures. 1) SiGe S/D of Si fin; 2) SiGe core pMOS; 3) SiGe cladding pMOS. 4) SiGe S/D on rGe pMOS.