Direct Bonding Mechanism of ALD-Al2O3 Thin Films

Monday, 6 October 2014: 14:40
Expo Center, 1st Floor, Universal 9 (Moon Palace Resort)
E. Beche, F. Fournel, V. Larrey (CEA, Leti, Minatec Campus), F. Rieutord (CEA, INAC), C. Morales (CEA, Leti, Minatec Campus), A. M. Charvet (CEA, LETI, Minatec Campus), F. Madeira (CEA, LETI), G. Audoit, and J. M. Fabbri (CEA, LETI, Minatec Campus)
Direct bonding is used to join two mirror-polished wafers without any additional material. This technique demonstrates to be more and more attractive for microelectronics, MEMS, or optoelectronic applications as example. In many of them, Silicon-On-Insulator (SOI) substrate is used including a SiO2 buried layer (BOX). Face to circuit performance request, SOI self-heating in these devices has to be improved, replacing BOX by adapted layers, for instance. The conciliation between the thermal and electrical properties has already pointed out different materials such as diamond, Al2O3, HfO2 or Si3N4 [1]. Atomic Layer Deposited (ALD) amorphous Al2O3 thin film seems to be very interesting but different problems as for instance debonding phenomena [2][3], or defect emergence [4][5][6] could appear during their elaboration which motivated our direct bonding mechanism study. In this work, comparative results between free surfaces and bonding configurations will be done in order to establish bonding behaviour of ALD Al2O3.A bonding mechanism will be discussed and proposed.

The study is carried out on 300mm, lightly p-doped Si wafers. Substrates have been oxidized by plasma or thermal treatment in order to create 1.5, 20 or 145nm SiO2 sub-layer. 20 nm-thick amorphous alumina (a-Al2O3) films were then deposited at low temperature (300°C) by ALD using TMA and H2O precursors. Some samples were annealed at various temperatures under nitrogen or oxygen atmosphere in order to crystallize the amorphous alumina. Due to low chemical resistance of the amorphous ALD Al2O3layer, the wafers were just rinsed with de-ionized water under megasonic power, dried and contacted to each other or directly to silicon wafers or oxidised silicon wafers at room temperature (RT) and atmospheric pressure. Bonding quality is analysed at room temperature and after various annealing temperatures.

After 400°C post bonding annealing, using scanning acoustic microscopy (SAM), a high defect density is observed for several bonding type (fig 1a) which is invisible using wafer-scale IR observations (fig 1b). In the specific a-Al2O3/a-Al2O3bonding, debonding could even occur after 500°C annealing. Bonded surface analyses exhibit inhomogeneous fracture and bubble traces at the bonding interface (fig 1c).

This paper will deal with bonding mechanism and the defect origin. We will highlight the role of water/hydrogen diffusion in the bonding process and the link that could be done with the well-known [4][7] defects which could appear during O2-atmosphere annealing of amorphous ALD Al2O3 free surfaces (fig2a) while no defect are seen under N2annealing (fig2b).

Using atomic force microscopy to measure the surface roughness, the electron beam microscopy to visualize the debonding interface, the anhydrous bonding energy measurements, the FTIR-MIR [8] to characterize the chemical interface evolution and the X-ray reflectivity for monitoring the interface electron density profile, all the different bonding structures achieved in this study have been analysed (preannealing, sublayer use…).

Based on known SiO2 hydrophilic direct bonding mechanisms [8], refined bonding mechanisms for amorphous a-Al2O3 bonding will be proposed. Therefore, defect free amorphous Al2O3bonding could be obtained overall the post bonding annealing temperature range (RT-1200°C) as shown for 300mm bonded structures (Fig 3).

One of the first applications of this work would be the elaboration of high quality SOI structure having this ALD Al2O3layer as an insulating layer.


The authors would like to thank SOITEC for its support.


[1] N. Bresson, et al. Solid-State Elect. 49, 1522-1528, 2005

[2] P. Ericsson, et al., ECS PV, 576, 1997

[3] C. de Beaumont, et al., Electro Soc. 3, 231-236, 2005

[4] M. Yokoyama, et al., Semi. Sci. Tech., 28, 2013

[5] D. Landru, et al., ECS JSS and Tech, 6, 2, Q83-Q87, 2013

[6] E. Beche, et al., Micro Techn (submitted)

[7] T. Nabatame, et al., JAP, 42, 7205-7208, 2003

[8] C. Ventosa et al., JAP, 104, 2008