Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

Germanium with higher electron and hole mobilities has been considered as a potential material for replacement of Si in CMOS transistors. However, due to the lower band gap of Ge compare to Si, bulk Ge devices suffer a high leakage current, which could be suppressed by employing a germanium on insulator (GeOI) substrate. High-κ-all-around asymmetrically-strained germanium nanowire trigate p-MOSFETs have exhibited the highest hole mobility recorded (1490 cm²/V.s) [1]. There are several approaches for the fabrication of GeOI substrates including separation-by-implanted-oxygen (SIMOX) [2], Ge condensation [3], liquid phase epitaxy [4], and wafer bonding [5]. Wafer bonding technique is advantageous among the other techniques due to its simplicity and potential for achieving high quality crystalline Ge layer.

In this work we present a method to fabricate relaxed and strained GeOI substrates using heteroepitaxy and layer transfer techniques. The goal is to produce high quality wafer scale GeOI platform for relaxed and strained Ge nanowire CMOS fabrication. GeOI substrates are designed and fabricated via wafer bonding and etch back process without intermediary chemical mechanical polishing (CMP) step. Low temperature bonding avoids strain relaxation, Ge diffusion and detaching due to thermal expansion coefficient differences.

  In this design, GeOI structure is achieved by epitaxial growth and conventional dry and wet-etch techniques. All the epitaxial layers in the process are grown using RPCVD Epsilon 2000 ASM reactor. The fabrication process for both structures starts with the epitaxial growth of a roughly 1 µm Si_0.96Ge_0.04 etch stop layer. In the strained GeOI design the process is followed by epitaxial growth of an intermediate relaxed SiGe buffer with a Ge content of 40-50 percent, then a strained Si etch-stop layer and finally pseudomorphic growth of a thin strained Ge layer on top (Fig. 1). In relaxed GeOI structure on 1 µm Si_0.96Ge_0.04 etch stop layer a rather thick Ge layer (~300 nm) is grown in two steps, first a low temperature (LT) Ge is grown with high defect density and then a high temperature (HT) high quality Ge layer is grown on top (Fig. 2). Once the epitaxial growth of the structures is finished, 10 nm Al₂O₃ is deposited on top the Ge layer using atomic layer deposition (ALD). Then the wafers are brought together in the atmosphere pressure for room temperature bonding. The etch-back process begins by thinning down the donor wafer using Applied Materials Centura deep trench Si etch chamber (etch rate ~7 µm/min ). The etching process stops on the Si_0.96Ge_0.04 etch stop layer using endpoint detection system. At that point, the Si_0.96Ge_0.04etch-stop layer is selectively etched in TMAH solution. Then in relaxed GeOI structure the 300 nm Ge layer is oxidized and chemically thinned, up to the desired thickness (Fig. 2). In the strained GeOI structure SiGe relaxed buffer layer is selectively wet etched using dHF(100H₂O:1HF):HNO₃:CH₃COOH (0.15:0.20:0.30) solution, and the strained Si layer is selectively removed in TMAH solution, leaving the strained Ge layer on Al₂O₃ (Fig. 1). Infrared (IR) image of the bonded wafers shows few voids at the interface and the bonding can withstand fast deep Si dry etching. X-ray analysis shows high quality well separated peaks for both structures and demonstrates the strain in top Ge layer (for the strained GeOI). The bonding strength will be measured using stress tester. The bonded interfaces will be observed by high resolution transmission electron microscopy (HRTEM). Topology of both Ge surfaces will be shown by atomic force microscopy (AFM).

In summary, processes for the fabrication of high quality, low defect, monocrystalline, relaxed and strained germanium on insulator substrates are developed and optimized. This technique can serve as a platform for the fabrication of high performance Ge devices. Acknowledgment

This work was supported by European Union ERC Advanced Grant 228229 OSIRIS.

Fig. 1) schematic image of the bond and etch back process for strained GeOI

Fig. 2) schematic image of the bond and etch back process for relaxed GeOI

[1]         J. L. H. et al., IEEE, p. 4, 2012.

[2]         T. Mizuno, et al., IEEE Electron Device Lett., no. 5, pp. 230–232, May 2000.

[3]         T. Tezuka, et al., Appl. Phys. Lett., no. 12, p. 1798, 2001.

[4]         M. Miyao, et al., Appl. Phys. Express, p. 045503, Apr. 2009.

[5]         G. Taraschi, et al., Solid. State. Electron., no. 8, pp. 1297–1305, Aug. 2004.