Interpretation of Defect States in Sputtered IGZO Devices Using I-V and C-V Analysis

Tuesday, 7 October 2014: 16:40
Expo Center, 1st Floor, Universal 4 (Moon Palace Resort)
T. Mudgal, N. Walsh, N. Edwards (Rochester Institute of Technology), R. G. Manley (Corning Incorporated), and K. D. Hirschman (Rochester Institute of Technology)
There has been significant progress in advancing the performance of IGZO TFTs; however device stability still remains a challenge.  While traditional materials and techniques used for silicon-based TFTs may not be applicable, the influence of defect states can be reduced by annealing.  The interpretation of non-ideal current-voltage (I-V) characteristics is not always unambiguous due to issues that may be related to carrier injection.  Capacitance-voltage (C-V) analysis provides complementary information that is valuable in separating the influence of material and interface defects from other factors that influence transistor operation.

In this work, bottom-gate, top-contact TFT structures and interdigitated capacitors fabricated using sputtered IGZO have been investigated.  Interdigitated capacitors, unlike one-dimensional capacitors, are much more representative of the actual TFT structure; specifically the channel region.  Annealing was performed at 300 - 400 °C in O2, N­2and air ambient conditions.  Silicon dioxide, aluminum oxide, and B-staged bisbenzocyclobutene-based (BCB) resins were applied as materials for back‑channel passivation.  Analytical measurements and both I-V and C-V results were used to refine a material model developed for TCAD device simulation [1].  The correlation between I-V and C-V characteristics will be presented.

[1]  T. C. Fung, C. S. Chuang, C. Chen, K. Abe, R. Cottle, M. Townsend, et al., "Two-dimensional numerical simulation of radio frequency sputter amorphous In-Ga-Zn-O thin-film transistors," Journal of Applied Physics, vol. 106, p. 084511, 2009.