On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes

Top candidate to further improve the performance of CMOS image sensors while keeping up with the market demands for thinner, lighter, and more sophisticated applications such as smartphones and tablets, is backside illuminated (BSI) image sensors. In BSI image sensors, maximal light coupling to the substrate is ensured by thinning down the non-sensitive part of the substrate. However, while trying to ensure a damage-free back layer for maximal detection capability, several technological and manufacturing challenges arise.

We have previously fabricated and reported the functionality of working BSI devices, with special emphasis given to backside passivation of BSI image sensors using laser anneal [1].

In this work, we zoom in the process details of these BSI devices; hence, we report and discuss key process integration developments in three main areas: wafer preparation and oxide-oxide bonding, wafer edge trimming, and substrate thinning.

In the first section, we discuss the impact of different oxide deposition techniques (native, thermal, PECVD, O3TEOS) and various cleans (water, SC1, MS6020) implemented on both carrier and device wafers. The importance of other required oxide pre-bonding treatment steps such as oxide CMP (using different slurries) and oxide sintering are investigated. We have also looked into rework possibilities such as re-oxide deposition and CMP of out of spec wafers, for increased process window. Further, the bonding tool pre-requirements for a successful oxide-oxide bonding of 200 mm BSI image sensor wafers are explained. 

In the second section, we demonstrate the importance of trimming down the wafer edge, as well as report on its technical aspects like mounting on dicing tape, trim method, choice of blade, failure mechanisms, and comparison on the edge trim before or after bonding.

In the third section, we describe and demonstrate the importance of different thinning techniques and their relative sequence such as grinding, doping selective Si wet etch, non-selective Si wet etch and Si CMP to ensure a uniform and nearly damage free back layer during the removal of the non-sensitive part of the substrate.

Bonding, edge trim and extreme wafer thinning are not ready available and implemented in many CMOS foundries. These processes are relatively new to imager fabrication and hence require mastering each step to achieve the yield requirements of an imager product. In this paper, we emphasize the importance of some process parameters while showing the available process window (figure 1).

References:

[1] K. Minoglou et al., “Evaluation of backside passivation using laser annealing in backside illuminated image sensors”, CMOS image sensors for high performance applications workshop, 2013 November 26-27,  Toulouse, France.

Figure captation:

Figure 1: SAM images of bonded wafers a) before and b) after pre-bonding optimization. c) SAM image showing the edge delamination observed for bonded wafers with several metal layers, and d) extreme edge trim case to ensure a void free process. Bonded wafer e) after Si thinning and f) with complete BSI imager sensor process having multiple metal layers.