(Invited) Wafer Bonding: An Integration Route for Hybrid III-V/SiGe CMOS on 300mm

Monday, 6 October 2014: 15:20
Expo Center, 1st Floor, Universal 9 (Moon Palace Resort)
L. Czornomaz, N. Daix, E. Uccelli, V. Djara, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori (IBM Zurich Research Laboratory), J. M. Hartmann (University of Grenoble - Alpes), and J. Fompeyrine (IBM Zurich Research Laboratory)
1. Introduction

As Si-CMOS scaling is becoming increasingly challenging, III-V compound semiconductors such as InxGa1-xAs (x≥0.53) (InGaAs) are receiving an increasing interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers.

III-V integration on Si by direct wafer bonding is considered as one of the possible paths towards this objective [3]. Our rationale is that (1) InGaAs-on-insulator can be fabricated with the appropriate critical dimensions and thermal stability, (2) source wafers can be fabricated on large diameter wafers with acceptable defect densities and (3) hybrid substrates can be used to fabricate simple CMOS circuits.

2. InGaAs-on-Insulator

A possible fabrication path for InGaAs-On-Insulator substrate is summarized. For demonstration purposes, the source substrate can simply be etched. A manufacturable process will however rely on the H-induced thermal splitting, as demonstrated in [3]. For thin layers as required for advanced CMOS, the thickness of InGaAs-o-I is below the critical value determined by the thermal strain up to 600°C. In addition, the interface energy at the Al2O3-Si bonding interface is almost 1 J/m2, larger than the one determined for SiO2-Si bonding in SOI wafers [4]. Such structures can therefore undergo high temperature processes such as the regrowth of highly doped InGaAs source and drain. The thermal stability is illustrated by showing that the regrowth of InGaAs do not degrade the structural quality of the underlying ultra-thin InGaAs-o-I. Functional self-aligned devices have been processed down to short gate length Lg=24nm, demonstrating the stability of such structures [5].

2. Large diameter source wafer

For VLSI integration, the bonding flow must be available for large diameters. As no InP substrate is available above 4”, the only possibility is to grow a virtual donor wafer onto a large diameter silicon substrate. Low defect density as well as very low roughness is required. In our internal work, GaAs deposition is performed by MBE on 200mm Ge/Si (001) substrate 6° off-cut, and subsequent pseudomorphic InxAl1-xAs grading buffer (x~ 0-0.65) allows reaching InP lattice-matching conditions. The formation of a thin InGaAs active layer completes the heterostructure that is compatible with the direct wafer bonding process. The best rms/TDD values reported so far are for GaAs 1nm/low-107cm-2 , and for InGaAs 2nm/mid-108cm-2. , close to the best value reported so far for Aspect Ratio Trapping methods. Excellent device metrics have been obtained on such heterostructures, supporting the idea that they can be used as donor wafers.

3. Hybrid circuits

Based on the previous results, the co-integration of fully depleted InGaAs and SiGe MOSFETs can be envisioned. Starting from an 8 nm thick ETSGOI wafer, a 6 nm thick InGaAs layer can be transferred as in [6]. Because of the low temperature used during wafer bonding, and due to the presence of the BOX, cross-diffusion between InGaAs and SiGe is inhibited. The n- and p- active regions are defined based on mesa definition in the InGaAs and SiGe layer. The rest of the process follows an ETSOI-like front-end where n- and p-FETs are processed simultaneously. Such an hybrid structure is shown, for which a simplified process has been utilized, including a common gate stack and metal source drain instead of raised source/drain. The device characteristics have been extensively reported in [6], and a typical inverter transfer characteristic has been obtained, leading to the first demonstration of hybrid CMOS circuits based on high mobility channels.

[1] J. Lin, D. A. Antoniadis and J. A. Del Alamo, IEDM Tech. Dig. (2012)

[2] M. Radosavljevic, G. Dewey, D. Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, S. Kabehie, J. Kavalieros, V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, H. W. Then and Robert Chau, IEDM Tech. Dig. (2011)

[3] L. Czornomaz, N. Daix, D. Caimi, M, Sousa, R. Erni, M. D. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart and J. Fompeyrine, IEDM Tech. Dig. (2012)

[4] N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa and J. Fompeyrine, S3S conference 2013

[5] L. Czornomaz, et al., Proc. ESSDERC 2013

[6] L. Czornomaz, et al., IEDM Tech Digest (2013)