(Invited) SOI-Type Bonded Structures for Advanced Technology Nodes

Monday, 6 October 2014: 13:40
Expo Center, 1st Floor, Universal 9 (Moon Palace Resort)
J. Widiez, J. M. Hartmann, F. Mazen, S. Sollier (CEA, LETI, MINATEC Campus), C. Veytizou (SOITEC), Y. Bogumilowicz, E. Augendre (CEA, LETI, MINATEC Campus), M. Martin (LTM, CNRS), F. Gonzatti, M. C. Roure, J. Duvernay, V. Loup, C. Euvrard-Colnat, A. Seignard (CEA, LETI, MINATEC Campus), T. Baron, R. Cipro, F. Bassani (LTM, CNRS), A. M. Papon, C. Guedj (CEA, LETI, MINATEC Campus), I. Huyet (SOITEC), M. Rivoire, P. Besson (CEA, LETI, MINATEC Campus), C. Figuet, W. Schwarzenbach, D. Delprat (SOITEC), and T. Signamarcheix (CEA, LETI, MINATEC Campus)
Bulk silicon device technologies are reaching fundamental scaling limitations. The 28nm and 22nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to 10nm node. Innovations will be necessary for lowest node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication (Fig. 1). 

High mobility materials are expected to replace silicon as the channel material: attention has been focused recently on the III-V and the Ge materials (Fig.1). Indeed, III-V semiconductors (such as GaAs, InP, InGaAs and InAs) have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass [3]. In order to avoid short channel effects, these “new” materials have to be transferred as thin layers on buried oxide layers.   

SOI substrates are fabricated using the Smart CutTM technology. This process, based on hydrogen implantation and wafer bonding, made it possible to transfer a thin layer of crystalline material from a donor substrate to another substrate. This versatile technique for thin layer transfer enables the fabrication of hetero-substrates with a large choice for the crystalline superficial layers, the buried layers and even the handle substrates (Fig. 2). For More Moore applications, this leaves the freedom to transfer Ge or III-V thin layer on an optimized buried oxide layer.

In this paper, we will present our latest work on advanced SOI substrates for sub-28nm technology node and on novel “on insulator” substrates for sub-10nm node. We developed GeOI (Fig. 3) and InGaAs-OI (Fig. 4) substrates in 300mm. It is otherwise possible, thanks to low temperature direct bonding, to combine 3D CMOS integration (thereby increasing transistor density) and high mobility channel devices : a monolithic and vertical co-integration of GeOI pMOSFETs stacked on SOI nMOSFETs [4] or a III-V-OI nMOSFETs stacked on a SiGeOI pMOSFETs [5] have already been demonstrated with functional inverters and SRAM cells.

Acknowledgments: the authors acknowledge financial support from the European Commission via the FP7-COMPOSE3 and from the French Government's Investissement d'Avenir program (eXact projet).

[1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] S. Takagi, IEEE TED, 2008 [4] P. Batude, VLSI 2009 [5] T. Irisawa, VLSI, 2013.