Innovative Solutions to Materials Challenges for High-Voltage SiC Power Devices

Silicon carbide (SiC) is a material of interest for high-temperature, high-voltage and high-power switching device applications. Key materials challenges inhibiting such devices include elimination of basal plane dislocations (BPDs) and enhancement of minority carrier lifetimes in the drift or blocking regions of the device.  Recent progress in addressing both of these issues is presented.

        BPDs are a major concern for the SiC bipolar devices required for high-voltage applications as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes. Many methods have been investigated to reduce the BPD density including pre-growth treatments, substrate orientation, growth parameters and growth interrupts. It has been shown that the conversion of BPDs to threading edge dislocations (TEDs) continues throughout the epitaxial growth process in 4° off-axis SiC material and that a minimum thickness of ~16 µm is required to convert all BPDs to TEDs. Here we show that optimizing a hydrogen etch of the substrate prior to epitaxial growth significantly enhances conversion efficiency in a thin highly doped n⁺ buffer layer (BL). IN this work, epitaxial layers were grown on 4° off-axis substrates in an Aixtron/Epigress VP508 horizontal hot-wall reactor using the standard chemistry of silane (2% in H₂) and propane.

        In addition, using various growth approaches, low-doped epitaxial layers of only 20 µm in thickness on a 5 µm highly doped buffer layer have demonstrated minority carrier lifetimes up to 4 µs, as measured by time resolved photoluminescence, without any pre- or post- processing treatment. Interface recombination likely dominates these measurements. We extend this approach by presenting new data investigating the non-uniformity of lifetime found on as-grown material under various conditions.

This work is supported by the Office of Naval Research