Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting

High demands for improved performance, better power consumption, and miniaturized devices prompted the migration to SOI technology. SOI fabrication process helps in achieving greater performance and offers less power consumption compared to the Bulk Si Process. In SOI fabrication technology, transistors are built on a Si layer grown on SiO2 (145 nm) insulating layer. The SOI is fabricated using the SMART CUT wafer bonding and layer splitting technology. The strained Si on insulator (sSOI) technology has recently been developed for high mobility channel devices [1-3]. Biaxial tensile strained Si layers grown on SiGe have attracted great attention for high performance CMOS devices. Strain engineering for mobility enhancement is an attractive option to improve CMOS device performance by introducing lattice strain into the Si channel. Epitaxial Si_1-xGe_x and most recently Ge-free bi-axially strained sSOI are among the leading candidates for higher mobility channel material.

In this paper, we have analyzed how the fabrication of very thin single crystal Si device films by wafer bonding and SMART CUT^TM film exfoliation technique is affecting their nanomechanical properties in comparison to bulk Si. Although both the handle wafer and the bonded thin device layer are single crystal Si, it turns out that their nanomechanical properties differ considerably. Using nanoindentation, we measured the properties of (SOI-88nm) and bi-axially tensile strained Silicon-on-Insulator (sSOI 15, 70, and 100 nm) and benchmarked the results against bulk Si. 

The results of Figure 1 indicate that the hardness of these films vary significantly. The field emission scanning electron microscopy (FE-SEM) image of Figure 2 represents an sSOI film of 100 nm thick.

References

1. C. Mazure and A.J. Auberton-Herve, Proc. of 35^th European Solid-State Device Research Conf. ESSDERC, p. 29 (2005)
2. T. A. Langdo, M. T. Currie, Z.-Y. Cheng, J.G. Fiorenza, M. Erdtmann, G. Braithwaite, C.W. Leitz, C.J. Vineis, J. A. Carlin, A. Lochtefeld, M. T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, Solid-State Electronics, 48 , 1357 (2004).
3. I. Cayrefourcq, A. Boussagol and G. Celler, in SiGe and Ge: Materials, Processing, and Devices, ECS Trans. 3, (7), 399 (2006)