(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges

The effectiveness of widely-used CMOS stressors, such as compressive stress liners and embedded source/drain is significantly decreased in the state-of-the-art CMOS as the gate pitch is scaled down and device architecture is transformed from planar to 3D non-planar architectures, such as FinFETs. The issue is more pronounced for FinFETs fabricated on the SOI substrates. It is well known that SiGe is a great candidate for p-type MOSFETs due to its intrinsic lower effective mass and better transport properties than Si and has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a key knob to adjust the PFET threshold voltage and performance enhancement [1, 2]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable transport (neither long-channel nor short-channel) benefit over Si and it is believed that the strain plays a significant role in high-performance (HP) SiGe channel pFETs [3]. The strain state in typical thin SiGe substrates grown on bulk Si or SOI is biaxial compression. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain (uniaxial for FinFET) where the effective mass is significantly lowered and higher hole velocities can be achieved. Hole transport can be significantly improved by increasing the Ge content as well as the built-in strain, while the second component (strain) has a stronger impact on the transport enhancement. However, higher-Ge content SiGe offers reduced bandgap and may result in increased gate-induced –drain-leakage (GIDL) and high off current due to increased band-to-band or trap-assisted tunneling. This brings concern for some CMOS applications, such as I/O devices and SRAM. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging and can cause significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short-channel on-state current at the target off-current at a scaled power-supply voltage, V_DD.

In order to experimentally investigate the device characteristics of SiGe FinFETs, we have fabricated strained-Si_1-xGe_x-on-insulator pMOS FinFETs with Ge fraction, x~0.3-0.5 using CMOS-compatible process flows which allow us co-integration with Si or strained-Si for n-type transistors. Highly-compressively-strained SGOI substrates were fabricated using Ge condensation processes and strain transformation to uniaxial was verified by Raman spectroscopy. A gate-first high-K/metal-gate flow with ion-implant-free raised-S/D and aggressively scaled fin and spacer dimensions has been developed to fabricate devices with aggressively scaled gate lengths [4].  A Si-cap-free scheme was developed for the interface passivation to allow CET scaling and eliminate the epitaxial related issues on the 3D architectures. We have observed that non-optimized passivation may result in relatively high interface trap densities and sub-threshold slopes (SS) around 75-80mV/dec for x~0.3 and over 80mV/dec for x~0.5. However, by optimizing the passivation process using a Si-cap-free approach, impressive SS=65mV/dec and 68mV/dec has been achieved for SGOI FinFETs with x~0.3 and x~0.5, respectively. Moreover, significant transport benefit in terms of mobility and drive current has been achieved due to the improved passivation [5]. As a result, we have reported superior mobility characteristic for SGOI pMOS FinFETs with x~0.5 over the state of the art Si, SiGe or relaxed-Ge FinFETs [6].

We have also investigated the short-channel GIDL characteristics of surface-channel strained-Si_1-xGe_x pMOS FinFETs. We have shown devices having a minimum GIDL current of 1nA/μm for x~0.3 and 20nA/μm for x~0.5 at an operating voltage of V_DD=0.8V and an operating temperature of 50°C. Temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling is the dominant leakage mechanism as compared to trap-assisted tunneling for both cases [7].

In summary, we have reported process integration and electrical characterization of SGOI FinFETs with aggressively scaled gate and fin dimensions and Ge content x~0.3-0.5 using an improved Si-cap-free surface passivation process. SiGe-OI FinFETs with x~0.3 can offer superior pMOS characteristics and are promising candidate for both high-performance and low-power applications. On the other hand, while SiGe-OI FinFETs with x~0.5 can offer extremely high mobility and high current drive and transconductance which is applicable to high-performance CMOS, their operation even at low V_DD could be a concern for low-power applications, similar to the state-of-the-art Ge FinFETs [8].

1. S. Krishnan et al., IEEE IEDM, 634 (2011).
2. C. Ortolland et al., IEEE IEDM, 236 (2013).
3. A. Khakifirooz et al., IEEE EDL, 34, 1358 (2013).
4. P. Hashemi et al., Symp. VLSI Tech., 18 (2013).
5. P. Hashemi et al., Symp. VLSI Tech., 18 (2014).
6. P. Hashemi et al., IEEE IEDM, 16.1 (2014).
7. K. Balakrishnan et al., IEEE DRC, 183 (2014).
8. B. Duriez et al., IEEE IEDM, 522 (2013).