(Invited) Monolithic Integration of III-V As- and P-Based Devices on Si through Direct MBE Growth and Using Lattice Engineered Substrates

Tuesday, 26 May 2015: 08:20
Conference Room 4M (Hilton Chicago)
D. Lubyshev, J. Fastenau, A. Liu, and Y. Wu (IQE PA)
Mainstream silicon (Si) CMOS technology is finally experiencing limitations of pure Si‑based material and process. For digital electronics, to extend Moore’s law, the industry increasingly is investigating alternative materials and technologies to enhance channel transport properties and reduce power dissipation for future generation transistor circuitry. Heterogeneous integration of compound III-V semiconductor devices on Si may realize high performance integrated circuits for analog and digital applications and can incorporate optoelectronic components for high-speed data transfer. Such integration provides the combined advantages of high volume production of Si-based electronic circuitry with superior high‑speed performance of III-V components. At IQE, we developed molecular beam epitaxy (MBE) growth processes for the production of high quality III-V based transistor structures monolithically integrated onto CMOS-compatible substrates by direct MBE growth on Si wafers and also by utilization of specialized Si-on-Lattice-Engineered-Substrate (SOLES) substrates.

 Through work with industry partners, IQE has grown InP-based high electron mobility transistor (HEMT) and quantum well field effect transistor (QWFET) structures directly on Si substrates by MBE. Following a high-K gate dielectric fabrication process, QWFET devices demonstrated high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at VDS=0.5V. [1] As part of a program funded by the US Defense Advanced Research Projects Agency, IQE developed a direct MBE growth approach of an InP‑based heterojunction bipolar transistor (HBT) structure on the SOLES substrates, and together with our collaborators successfully created clusters of high-speed III-V HBT circuitry monolithically integrated side-by-side with Si CMOS on the same wafer. [2]

            In this paper, we will discuss structural and electronic properties of epitaxial device material, including dislocation filtering in the mismatched metamorphic buffers, and compare performance of devices fabricated on Si with reference material grown on lattice-matched InP substrates.

[1] Radosavljevic, M.; Chu-Kung, B.; Corcoran, S.; Dewey, G.; Hudait, M. K.; Fastenau, J. M.; Kavalieros, J.; Liu, W. K.; Lubyshev,D.; Metz, M.; Millard, K.; Mukherjee, N.; Rachmady, W.; Shah, U.; Chau, R. (2009), IEDM Tech. Dig., p.13.1.

[2] W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E. Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek, and N. Daval, J. Crystal Growth, 311, 1979 (2009).