(Invited) Monolithic Integration of III-V Semiconductors by Selective Area Growth on Si(001) Substrate: Epitaxy Challenges & Applications
Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8% between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active layers on Si. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy.
We report here on the growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.
As a conclusion, this study of III-V selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on (001) oriented Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is original and obviously confirm the potential of this heterogeneous integration option for high mobility logic devices, and photonic applications on a common Si platform.