Pulse Width Modulation for Reducing Pulsed MOS Capacitor Measurement Time

Carrier lifetime in silicon is a direct measure of its deep-level defect density. This parameter is therefore widely used for process screening purposes to check for unwanted contaminations such as metallic impurities. The dynamics of semiconductor industry requires the development of novel approaches to reduce the measurement time of commonly established carrier lifetime measurement techniques for more efficient screening in process lines. The pulsed MOS capacitor (MOS-C) is the most popular technique for measuring the generation lifetime (τ_g) where τ_g is being extracted from the capacitance transient response (C-t) of a MOS capacitor device when pulsed from accumulation into deep-depletion and as it moves from the non-equilibrium deep-depletion into the inversion. Although accurate and easy to implement, the pulsed MOS capacitor takes a long time to accomplish. For clean wafers the time for a single measurement can easily reach several hours. This becomes specifically problematic when the goal is to map the whole wafer area. Many attempts have been made to reduce the lifetime measurement times. The challenge, however, is to maintain the accuracy while trying to reduce the test time. It will showed that by using a dynamic pulse train and exploiting the pulse width, the pulsed MOS-C technique can be implemented not only to reduce the measurement time. If the accumulation pulse in the pulsed MOS technique is applied at a high frequency the device response will become substantially short resulting in a reduced measurement time. Interestingly, this approach will not cause any compromise in the accuracy with which the lifetime is measured.  TCAD simulations and experimental results will be presented to show the effect of the accumulating pulse width on the C-t transient of a typical MOS device.