Ion Implantation Applications for Advanced Device Scaling

In the past decade, the surge of mobile devices has been tremendous. These novel mobile devices have all functionalities to communicate as well as gaming, computing capabilities etc. Obviously with such enabling features, mobile devices are a very significant part of the semiconductor market. To address the stringent requirements in terms of battery lifetime, device speed and scaling, the mobile devices processing needed innovations. To achieve these, novel processing techniques in the front end of line (e.g., strained silicon channel, High-K Metal Gate) and novel contact materials for back end of line have been implemented. In addition, the process margin is becoming a key factor as the cost and complexity of making devices is increasing. One dramatic change to address device scalability is the moved to Multigate architecture such as the FinFET (Field Effect Transistor) or GAA (Gate All around Transistors). In fact, the FinFET architecture enables to virtually increase the gate length of the device leading to better electrostatic performance.

For FinFET device, due to its three dimension architecture, the junction formation has some unique process requirements. Unlike planar devices, FinFET device requires side wall doping as well as excellent control of junction planarity. In addition, due to the small volume involved with narrow Fin, controlling the Fin damage is becoming a key challenge. To address these, damage engineering for tilted beamline implantation as well as plasma doping approaches have generated great interest. The paper demonstrates the benefits of these novel implantation concepts using different metrologies and device structures. We discuss that these novel implant techniques can also be applied to other applications to further improve FinFET device performances.

In order to achieve the multi-threshold voltage (Vth) needed for SoC applications, the work function tuning by implantation is of great interest. Several ideas have been discussed in literature for channel and/or metal gate Vth tuning and are reviewed in this paper.

Another key area of interest is the reduction of the device contact resistance. From an implant perspective, several approaches have been reported such as pre-silicide pre-amorphization technique, Schottky Barrier Height (SBH) reduction, or Dopant Segregation Schottky (DSS). We demonstrate that a combination of these contact implant techniques along with advanced annealing provide ways to meet the contact resistance and uniformity need.

 To further increase channel mobility, new channel materials are being considered to further boost device performance. For PMOS, the move to SiGe or Ge channels is very attractive, however formation of such Fin channels is a challenge. From a diffusion perspective, the main p-type dopant (Boron) has a lower diffusivity as Germanium concentration increases, which may benefit Short Channel Control. However, for NMOS devices, n-type dopants (Arsenic and Phosphorus) diffuse faster than in silicon as well as have lower solubilities. This results in a strong challenge in forming a highly active as well as defect-free  junction. We will demonstrate that damage engineering via a combination of novel implant and anneal technologies for junction, damage, and strain will become even more critical for these novel channel materials.

Finally we will review the change of architecture to Gate All Around and briefly discuss the multiple implant applications for those new devices.