Heated Ion Implantation Technology for High Performance Metal-Gate/High-k CMOS SOI Finfets

Tuesday, 26 May 2015: 14:20
Conference Room 4M (Hilton Chicago)
W. Mizubayashi (National Institute of AIST), H. Onoda, Y. Nakashima (Nissin Ion Equipment Co., Ltd.), Y. Ishikawa, T. Matsukawa, K. Endo, Y. Liu, S. O'uchi, J. Tsukada, H. Yamauchi, S. Migita, Y. Morita, H. Ota, and M. Masahara (National Institute of AIST)
1. Introduction

Thinning of the fin channel is a key technology for CMOS FinFET scaling. For sub-14nm- node FinFETs, the fin channel becomes thinner than 10 nm. Furthermore, lowering of the sheet resistance (Rs) in the source/drain extension (SDE) is essential for performance improvement [1]. However, in the case of conventional I/I, it is difficult to reduce Rs because conventional I/I generally causes poly-crystallization and/or crystal defects to be formed in ultrathin fin region, even after activation annealing [2, 3]. This problem is particularly severe for SOI FinFETs. Recently, a novel I/I technology called heated I/I has been proposed. By using the heated I/I technology, the crystallinity of the implanted layer for Si is maintained during heated I/I, and defect-free crystal can be realized by activation annealing [4, 5]. Furthermore, it has been reported that the Ion-Ioffcharacteristics are improved in bulk Si-channel nMOS FinFETs by heated I/I [6].

In this paper, we report heated I/I technology for high-performance metal-gate/high-k CMOS SOI FinFETs.

2. Experimental

Both nMOS and pMOS SOI FinFETs were fabricated. (110) fin channel was formed on (100) SOI substrate. Doped-poly-Si/TiN/HfO2/SiO2 gate stacks were formed, patterned, and etched. SDE was formed by room temperature (RT) or 500oC I/I. As+ or BF2+ was implanted at 5keV with total doses of 2x1015cm-2. RTA was performed at 915oC for 2s. Finally, the back-end process was carried out.

3. Results and Discussion

To understand the crystal condition in the ultrathin fin region after heated I/I, we investigated the crystallinity of the SOI layer after RT and heated I/I by cross-sectional TEM observation (Figs. 1 and 2). The I/I was performed under the same conditions as those for the SDE formation in FinFETs (Figs. 1(a) and 2(a)). In the case of RT I/I, the SOI layer is fully amorphized by I/I (Fig. 1(b)), and polycrystals and twins are observed even after annealing (Fig. 1(c)). Since there are no seed crystals in the SOI layer after I/I, the implanted region cannot be crystallized by activation annealing. On the other hand, in the case of heated I/I, the crystallinity is maintained in the SOI layer after I/I (Fig. 2(b)). The crystal perfectly recovers by activation annealing (Fig. 2(c)). These results indicate that the defect-free SDE can be formed in ultrathin fin region by heated I/I.

We investigated the impact of heated I/I on the SOI FinFET performance. Figures 3 (a) and (b) show the Ion distribution in the nMOS and pMOS FinFETs, respectively, processed by RT or heated ion implantation. For the nMOS FinFETs, the 50% Ion value of heated I/I is about 7% higher than that of RT I/I. Also, for the pMOS FinFETs, the 50% Ion value in the case of heated I/I is about 1.5% higher. The resistance (Rsd) of the SDE becomes lower in the case of heated I/I (Fig. 4), owing to perfect crystal recover [7]. This is the main reason for the improvement in Ionby heated I/I. Thus, by using heated I/I, the SOI FinFET performance is improved as compared with conventional RT I/I.

4. Conclusion

Heated I/I contributes to the formation of the defect-free SDE in ultrathin fin region and is effective for improving the performance of ultrathin FinFETs. Thus, heated I/I technology is promising for SDE formation in future SOI FinFETs.


[1] C.-H. Jan et al., IEDM Tech. Dig., 2012, p. 44.

[2] M. J. H. van Dal et al., 2007 Symp. on VLSI Tech. Dig. (2007) 110.

[3] R. Duffy et al., ESSDERC (2008) 334.

[4] H. Onoda et al., Ext. Abs. the 13th Int. Workshop on Junction Tech. (2013) 66.

[5] H. Onoda et al., Ext. Abs. the 14th Int. Workshop on Junction Tech. (2014) 126.

[6] M. Togo et al., Symp. on VLSI Tech. Dig. (2013) T196.

[7] W. Mizubayashi et al., IEDM Tech. Dig. (2013) 538.