(Invited) Plasma Etching Technology Challenges for Future CMOS Fabrication Based on Microwave ECR Plasma

Tuesday, 26 May 2015: 15:00
Conference Room 4M (Hilton Chicago)
M. Izawa, M. Tanaka, N. Yasui (Hitachi High-Technologies Corp.), and M. Morimoto (Hitachi High-Technologies Taiwan Corporation)
As dimensions of semiconductor devices shrink further into the nanometer range, transistor performance is improved not only by scaling and adopting boosting technology, but also by adopting new channel material and structure. It is also required to reduce power consumption for mobile devices. In MOS logic devices, 3D-trasistor (FinFET) was adopted to improve switching property. When fabricating, more accurate and higher aspect ratio patterning is required, e.g. fin width reaches 3.7 nm at the 5nm node, where nanowire FET and Ge/III-V channel materials are other candidates [1]. Thus, required accuracy will reach atomic level in the etching process. To realize nm scale etching, new etching process functions are necessary to suppress wiggling, roughening, and degradation of etched layer. At the same time, reasonable productivity is required for mass production.

To improve etched profiles, we have been investigated and improved microwave ECR plasma etch tool, e.g. installation of time modulation (pulsing of RF bias, discharge, and gas) technologies, accurate power control of wafer RF bias, end-point monitor, and so on. TM bias (wafer RF bias pulsing) technology is already    used in semiconductor fabrication [2]. Lower RF bias power and zero bias condition were effective for extremely high-selective etching.

Microwave ECR plasma tool seems to have good affinity to pulsing discharge because it was designed to avoid the drift of plasma density. By using the pulsing discharge, wiggling was suppressed dramatically in DSA mask etching [3].

  Gas pulsing technology was also investigated for fin etching. Etching progress and sidewall protection steps were changed cyclically without interruption of the discharge. It was found that etched profile (vertical, etch front flatness, and mask selectivity) was improved [4].

  Atomic level precision etching is required in future MOS device fabrication where etched material, etch stop layer, and structure become more complicated. It will be necessary to control lower ion incident energy with vertical direction, lower the gas dissociation to reduce aggressive radical generation and reduce sidewall deposition. We believe multi-pulsing technology (discharge, bias, and gas) and low bias power control at low pressure operation are key technologies to realize atomic level precision etching.

[1]    ITRS 2013.

[2]    T.Ono el al, JJAP. 38, 5292 (1999).

[3]    M. Morimoto et al., SPIE 2014 [9054-18].

[4]    M. Tanaka et al., JSAP Autumn meeting, 19p-S10-7, 2014.