Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

Tuesday, 26 May 2015: 17:00
Conference Room 4M (Hilton Chicago)
M. Engelhardt, J. Baumgartl, G. Denifl, G. Ehrentraut, M. Kuenle, M. Stadtmueller, S. Werner (Infineon Technologies Austria AG), D. Crippa (LPE Milano), and M. Kraft (CTR Villach)
Transferring power technologies from 200mm silicon substrates to 300mm provides challenges with regard to very special substrate materials, process equipment, and unit processes in addition to those faced by a similar transfer of CD driven commodity products as DRAMS and MPUs. Due to the fact that the current path leads vertically through the substrate and that the final substrate thickness thus determines the figure of merit, the electrical resistance of the device in on-state, ultra-thin wafer handling for wafer backside processing is a further specialty and hence challenge for power semiconductors manufacturing. Current furnace equipment for standard CMOS is capable of processing at temperatures up to 1000°C whereas power technologies require furnace temperatures up to 1200°C which requires hardware adaptation of the tools to comply reliably with these requirements. Some applications furthermore require temperature uniformity within very narrow intervals across the wafers within wafer batches. Wafers with polysilicon films on the wafer backside for impurity gettering are so far only available on 200mm. Such gettering films were deposited and analytically assessed with regard to their gettering capabilities. The extremely high doped wafer substrates for manufacturing power devices are not available yet from the suppliers in both sufficient quality and quantity to start 300mm power semiconductor activities. These substrates have to be manufactured by the semiconductor manufacturer by epitaxial growth. In addition to severe modifications of the epitaxial reactors and the provision of the complete infrastructure that allows running such processes under safe operation conditions unit process development is very challenging. Simultaneous achievements of both supreme uniformity of thick epitaxial layers and of the dopant distribution therein is key to allow perfect pattern generation and transfer and identical electrical device performance respectively all across the wafer until the very wafer edge to take full advantage of the productivity advantage of large diameter wafer processing. All the activities to improve tools and hence processes, were severely supported by equipment and process simulation. To boost productivity additionally to processing 300mm diameter wafers the use of a batch epitaxial tool has been envisioned for the growth of very thick and high resistivity silicon for IGBT applications. All the tool and process learning done on a 5-wafer 200mm batch tool will be used for the design and manufacturing of a similar tool type processing 300mm substrate. For this application high focus was posed on the reduction of sliplines, irregularities in film growth with atomic scale heights, resulting from non-uniform temperature coupling to the substrates in process. While critical CDs in high end products differ by almost an order of magnitude between power semiconductors and standard CD driven CMOS technologies, the tolerated CD uniformities are rather comparable. This finally requires for pattern transfer advanced plasma etch equipment with all the “knobs” to address wafer center and wafer periphery individually regarding etch rate, profile shape, and CD to achieve lowest center-edge non-uniformities. The various tool and process aspects of 300mm power semiconductor manufacturing will be addressed and reviewed in this talk.

The work has been performed in the project EPT300, co-funded by grants from Austria, Germany, Italy, The Netherlands and the ENIAC Joint Undertaking.