Influence of Annealing Condition on TSV Pumping and Microstructure Evolution

Stacking of ICs using three-dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnection latency, and power dissipation while enhancing performance. Through silicon vias (TSVs) are regarded as a key enabling technology for 3D IC integration which assists in the realization of highly miniaturized and complex next-generation systems. Due to the thermal expansion (CTE) mismatch between copper and silicon, the copper in silicon vias tends to pump up as a result of thermal-mechanical stress during the post fabrication processes and/or during the lifetime of chip usage. One way to minimize or get rid of copper pumping is through heat treatment, for instance annealing or aging. The TSV wafers could be annealed right after copper plating process, or after chemical mechanical polish (CMP) process, or both. The residual stress might be thoroughly released by repeating annealing and CMP processes several times, however, the cost for fabricating the TSVs is increasing drastically, which is mainly attributed to the use of expensive CMP. To lower down the cost and minimize the CMP steps is one of the concerns from industry. In this paper, we report the thermal mechanical assessment of Cu pumping treated at different annealing conditions. moreover, the impact of different integration approaches on the TSV pumping behavior is also investigated. The finite element analysis method, ANSYS, is used to model and simulate the copper pumping at different temperatures, as shown in Fig.1. The pumping is measured by optical profiler, BRUKER ContourGT-X3, as shown in Fig.2. It has been found out that the copper grain size increases with annealing temperature, which is potentially contributed to larger protrusion. The preliminary results show that the annealing after copper plating process affects the microstructure evolution and pumping of TSVs.