(Invited) Record-Performance In(Ga)As MOSFETS Targeting ITRS High-Performance and Low-Power Logic

Tuesday, 26 May 2015: 11:20
Conference Room 4M (Hilton Chicago)
M. J. Rodwell (University of California Santa Barbara), C. Y. Huang, S. Lee, V. Chobpattana, B. Thibeault, W. Mitchell, S. Stemmer, and A. Gossard (University of California, Santa Barbara)
We review recent development of In(Ga)As-channel MOSFETs. Low-effective mass InAs and InGaAs channels, combined with thin gate dielectrics, provide high transconductance, but off-state leakage can be high due to band-band and source-drain tunneling currents.  This leakage is reduced through thin 2.5-3nm channels, and through InGaAs or wide-bandgap InP vertical field spacers in the raised, regrown source and drain.  Planar UTB devices with 2.7nm thick strained InAs channels and lightly-doped InGaAs spacers in the raised regrown source and drain provide, at 25nm gate length, record 0.5mA/µm on-current at 100nA/µm off-current  (ITRS HP specification) and 500mV VDD.  1 µm gate length FETs show 61mV/decade subthreshold swing at 0.1 Volts VDD.  Targeting the ITRS LP specification, we have developed InGaAs-channel MOSFETs with lightly-doped InP wide-bandgap spacer layers in the raised source and drain.  At 30nm gate length, these show a minimum 60 pA/µm off-current, approximately 100:1 smaller than a similar device using InGaAs source/drain spacers. A FET using InP spacers,  with 45 nm gate length, shows  0.15 mA/µm on-current at 1nA/µm off-current  (ITRS GP specification) and 500mV VDD.  We will discuss ongoing efforts to further increased on-current and decrease off-current in short-gate-length III-V MOSFETs.