(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs

Tuesday, 26 May 2015: 10:40
Conference Room 4M (Hilton Chicago)
R. T. P. Lee, W. Y. Loh, R. Tieckelmann, T. Orzali, C. Huffman, A. Vert (SEMATECH), G. Huang, M. Kelman, Z. Karim (AIXTRON), C. Hobbs, R. J. W. Hill, and S. S. Papa Rao (SEMATECH)
III-V semiconductors have emerged as a leading candidate to replace Si as channel material in future low power logic applications. To realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (REXT) be minimized. Among the different components of REXT, contact resistance (RC) between metal and source/drain (S/D) junctions has become a critical area of focus to lower REXT. Historically, multi-layered Au-based metal contacts (e.g. Au/Ge/III-V) were used in III-V processing. However, the renewed interest in III-V semiconductors for CMOS has attracted an increasing interest by many to develop Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it is a self-aligned process and it offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Si/Ge/III-V). In this paper, we will review these technology options for RC reduction and present some of our recent results on contact/junction engineering to lower RC in III-V transistors.