(Invited) The Assessment of Border Traps in High-Mobility Channel Materials

Tuesday, October 13, 2015: 14:30
105-B (Phoenix Convention Center)
E. Simoen (imec), A. Alian, H. Arimura (Imec), D. Lin, H. Mertens (imec), J. Mitard (Imec), S. Sioncke (Imec), W. Fang (Imecas), J. Luo (Imecas), C. Zhao (Institute of Microelectronics, CAS), A. Mocuta, N. Collaert, A. Thean (Imec), and C. Claeys (Imec)
While the issues of Fermi level pinning by interface states at the dielectric/semiconductor interface has first attracted the concern of device engineers working on high-mobility channel devices, more and more attention is going nowadays to the so-called border traps (BTs) at some distance from the interface in the gate dielectric. According to their definition [1] they are able to communicate with the inversion layer in a MOS devices with time constants on the order of 1 ms and higher. As such, they will contribute to the frequency dispersion and hysteresis in capacitance-voltage and transconductance characteristics [2] and generally dominate the low-frequency noise spectrum [3]. Historically speaking, the 1/f noise in MOSFETs has always been interpreted in terms of trapping/detrapping towards BT (Fig. 1), whereby in many cases, pure elastic tunneling was assumed, yielding a simple relationship between the trap depth z and the noise frequency f, which is based on the tunneling parameter at. The latter mainly depends on the tunneling barier Φit at the interface and the tunneling effective mass mox [3]. Based on that, several methods to derive a BT density profile from a noise spectrum have been developed; an example is given in Fig. 2 for the spectrum obtained on a Si-passivated Ge pMOSFET.

            It is the intension of this work to illustrate the 1/f noise method for oxide trap profiling in high-mobility channel devices with a high-k gate stack. As shown in Fig. 3 for InGaAs/InP/Al2O3 nMOSFETs, quite uniform trap density profiles have been obtained, irrespective of the architecture, i.e., buried channel with InP cap or surface channel (InP etched) or the use of surface passivation with S [4]. On the other hand, the absolute value of the trap density strongly depends on pre- and post-high-k deposition treatments. While there is quite some literature on the LF noise of Ge pMOSFETs with silicon passivation, little results have been reported on alternative gate stacks or n-channel Ge MOSFETs. As shown in Fig. 4, the noise spectrum for a Ge nMOSFET with GeOx/Al2O3/HfO2 gate stack is close to 1/f, yielding a uniform profile, according to the constant fxSI function. It corresponds with a high NBT in the range of 6×1019 cm-3 eV-1, indicating a rather poor gate stack quality [5]. Finally, the impact of inelastic tunneling in the modeling of BT profiles from 1/f noise spectra will be discussed and a possible internal depth versus frequency calibration will be outlined [6].


[1] D.M. Fleetwood, IEEE Trans. Nucl. Sci., 39, pp. 269-271 (1992).

[2] D. Lin et al., in IEDM Tech. Dig., The IEEE (New York), pp. 645-648 (2012).

[3] E. Simoen, H.-C. Lin, A. Alian, G. Brammertz, C. Merckling, J. Mitard and C. Claeys, IEEE Trans. Device and Mater. Reliability, 13, pp. 444-455 (2013).

[4] M. Scarpino, S. Gupta, D. Lin, A. Alian, F. Crupi, and E. Simoen, IEEE Electron Device Lett., 35, pp. 720-722 (2014).

[5] W. Fang, E. Simoen, H. Arimura, J. Mitard, S. Sioncke, H. Mertens, A. Mocuta, N. Collaert, J. Luo, C. Zhao, A. Thean, and C. Claeys, submitted for publication in IEEE Trans. Electron Devices.

[6] E. Simoen, J.W. Lee and C. Claeys, IEEE Trans. Electron Devices, 61, pp. 634-637 (2014).