Quantitative Characterization of Near-Interface Oxide Traps in 4H-SiC MOS Capacitors by Transient Capacitance Measurements
The characteristics of SiC MOS devices are often suffered from the effects of near-interface oxide traps, however, the quantitative analysis method of those traps has not been established. In this study we propose a method to estimate their density by transient capacitance measurement. We assume the oxide trap model , in which carriers in semiconductors interact with the traps in oxide by tunneling, with a widely-spread response time of the traps, due to the variation of the tunneling distance between the interface and the traps.
2. Characterization method
Transient response of capacitance (C-t) gives the information of trapping behaviors of the carriers in MOS capacitors [2-3], since the change of amount of trapped charges shifts the C-V curve. In this study we employed the MOS capacitors fabricated by thermal oxidation of n-type 4H-SiC. The gate bias on a capacitor was kept in accumulation state (Vg=Vtrap) for 100 sec to fill the traps, before a sudden shift to flatband state (Vg=Vmeas) to observe the C-t characteristics. Taking account of widely-spread response time of the traps due to their depth distribution in oxide, the time-dependent change of capacitance would be described by extended-Debye relaxation model  instead of a conventional relaxation with a single time constant, as |C(t)-Ceq|≈|DC0|exp (-(t/τeff)β), where Ceq is the capacitance in thermal equilibrium, β is the stretched exponential factor (0<β<1) of response time, τeff is the effective relaxation time of the group of traps with distributed response time, and DC0 is the total change of capacitance.
C-t characteristics at 200K and 300K were fitted by the above equation to determine DC0, from which the amount of trapped charges in near-interface traps per area (Qox) was estimated by assuming that the distance of the traps from the interface is significantly shorter than the film thickness. Note that low temperature slows down the de-trapping process by a few orders because of the change of the Fermi-Dirac distribution. Even though our measurement system detects only relatively slow response (≥0.1 s), low temperature measurement enables us to evaluate the traps locating very shallow region(~ a few ongstroms from the interface).
3. Results and Discussions
The observed C-t characteristics were well-fitted by the extended-Debye relaxation model as desribed above. The lower temperature measurements resulted in larger DC0 which is indicating more traps exist in the region closer to the interface. By changing the Vtrap while unchanging the Vmeas, we can vary the width of energy region of the traps contributing to the C-t characteristics. From the SiC surface potential dependence of Qox, we can deduce the effective density of states (Dox) of the near-interface traps. We employed two kinds of MOS capacitors with different interface state density (Dit): ~1012 cm-2eV-1 and ~1011 cm-2eV-1 at 0.2 eV below conduction band edge. For the near-interface oxide traps in shallow region (measured at 200K), we could detect Dox of 3-4×1012 cm-2eV-1 for the higher Dit sample, but only ~5×1011 cm-2eV-1 for the lower Dit sample. These traps are estimated to locate at a few angstroms distance from the interface, taking account of the tunneling mass of electrons in SiO2. On the other hand, both of the two samples showed relatively less density of traps for the deep region (measured at 300K), in the order of 1011 cm-2eV-1. The location of the traps detected at 300K is estimated to be ~ 1 nm depth from the interface. These results indicates that the oxide trap density in shallow region is significantly sensitive to the preparation condition of SiC/SiO2 interface.
The method to determine the near-interface oxide trap density in MOS capacitors from transient capacitance characteristics was proposed and demonstrated for 4H-SiC MOS capacitors, by taking account of the wide distribution of distance between the traps and the interface. The effective state density of the near-interface traps was estimated to be 1011 ~1012 cm-2eV-1 for shallow location from the interface but ~1011 cm-2eV-1 for deep location for our MOS capacitors.
This work was partly supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO), and by JSPS KAKENHI.
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