Tunneling Current Induced Frequency Dispersion in the C-V Behavior of Ultra-Thin Oxide MOS Capacitors

Tuesday, October 13, 2015: 16:40
105-B (Phoenix Convention Center)
C. F. Yang (National Taiwan University) and J. G. Hwu (National Taiwan University)
The accuracy of using high-low frequency capacitance-voltage (C-V) curves to extract interface trap properties for ultra-thin oxide metal-oxide-semiconductor capacitors (MOSCAPs) is of concern due to tunneling current effect. In this work, it was found that tunneling current gives rise to the enhancement of C-V frequency dispersion.

   CV curves for ultra-thin oxide MOSCAPs (Al/SiO2/p-Si/Al) with various oxide thicknesses are shown in Figure 1. The abnormal behavior in depletion bias region for the low frequency CV curves is obvious. Conventionally, this frequency dispersion can be attributed to the existence of interface trap density (Dit) at the SiO2/Si interface. Compare to the thick oxide device of 2.7nm, the frequency dispersion of thin oxide one of 2.0nm is so large that it was hard to believe that all the dispersions come from simply Dit. We suppose that there are other effects besides Dit that would result in huge frequency dispersion in CV curves. The TCAD simulation without adding Dit but with tunneling mechanism in the model was implemented for MOSCAPs to support our assumption. From the simulation results in Figure 2(a), obvious humps appear in the low frequency CV curves. These hump increases as oxide thickness decreases (Figure 2(a)) or frequency decreases (Figure 2(b)). This trend is the same as the frequency dispersion of the experimental result. Most important of all, all the simulations are performed on MOSCAPs without Dit. This result implies that frequency dispersion of CV curves in ultra-thin oxide MOSCAP is not simply caused by the response of the carriers in silicon substrate to the interface trap level. The high-low frequency method is therefore improper to be used to extract Ditin ultra-thin oxide MOSCAPs.

    The simulation results show that for thicker oxides, the humps decrease. It is known that large tunneling probability plays an important role in ultra-thin oxides. Therefore, it was accepted that tunneling current in thin oxide is the cause of these humps. The band diagrams of device structure (Al/SiO2/p-Si) in the depletion bias region (VFB<VG<0) are shown in Figure 3. For ultra-thin oxides, minority carriers (electrons) would inject from metal gate to silicon which create access minority carriers in silicon. When capacitance was measured, these carriers can respond to the ac signal via tunneling path and create additional capacitance. Lower frequency makes the excess minority carriers respond more to the ac signal and results in larger hump in lower frequency.

   Although the origin of the additional capacitance is known, the reason why the additional capacitance appears as a peak is still unknown. To find the solution, the detailed distribution of excess carriers in the silicon was explored. Excess carriers injected from metal gate are distributed either in (Qinversion) or out of (Qdiffusion) the depletion region. Both can be extracted from TCAD simulation results.  Figure 4(a) shows the contributions of these two kinds of charges to the capacitances, i.e. Cinversion and Cdiffusion. The excess capacitance in the depletion region is much greater than that out of the depletion region. Since then, Cdiffusion can be ignored. Also, Figure 4(b) shows that the peak of the Cinversion is in coincidence with the peak of CV curve. As the result, it is believed that Cinversionis of importance to the appearance of CV dispersion.

   In reality, the direct tunneling is not the only tunneling mechanism in ultra-thin oxide. Since real device contains Dit more or less, trap assisted tunneling (TAT) exists in real device which means this TAT induced frequency dispersion is also related to the Dit. Nonetheless, the concept of tunneling induced CV dispersion is totally different from the conventional. The carriers passing through the interface states are not from silicon bulk, but from metal gate. These carriers would also partly contribute to the inversion charge which result in additional capacitance and make considerable error to the high-low frequency method in extracting Dit.

   This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

Figure Captions:

Figure 1. CV curves for MOSCAPs with various oxide thicknesses.

Figure 2. TCAD simulation for MOSCAPs with (a) various dox’s at 1kHz and (b) various frequencies for dox=2.0nm.

Figure 3. Band diagrams of Al/SiO2/p-Si structure operating in (VFB<VG<0) for (a) thick oxide and (b) ultra-thin oxide.

Figure 4. (a) Cinversion and Cdiffusion versus VG curves and (b) comparison between CG and Cinversion versus VGcurves.