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Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region

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_{off }ratio compared to conventional MOSFETs [4]. A number of studies based on simulations and analytical solutions have been performed to anticipate the performance of symmetric JLFETs [5-7]. However, a complete analytical treatment for both symmetric and asymmetric double gate JLFETs is necessary to make a comparative study of their performance. In this work, we propose a physically based analytical model of 2D electrostatic potential in the subthreshold region applicable for different structures of JLFET.

The schematic cross-sectional view of an n-type double gate JLFET considered in this work is shown in figure 1. The thickness of the source and drain regions are assumed to be zero for the sake of simplicity of modeling. The source and drain electrodes are shown to be present at the two side of the bulk silicon layer which is heavily doped with n-type impurity.

Figure 2 shows the analytical expression of 2D electrostatic potential in the channel region of double gate JLFET. In order to obtain the equation, we analytically solve 2D Poisson’s equation in the channel region using cubic approximation with appropriate boundary conditions. This analytical solution is valid in the subthreshold region of operation for both symmetric and asymmetric double gate JLFETs with similar and dissimilar gate bias configurations. α_{y }and β_{y }in the equation depend on the physical parameters and position along Y-axis which are not shown in the figure. Figure 3 and 4 show the surface plot of 2D channel potential distribution for symmetric and asymmetric double gate n-channel JLFET respectively. In this work we consider symmetric structure with P+ polysilicon as both gate electrodes and asymmetric structure with P+ polysilicon and Ni metal as top and bottom gate electrodes respectively.

For a fully depleted double gate JLFETs, the threshold voltage is reached when a portion of the channel is no longer depleted, such that bulk current flows through a neutral path. The threshold voltage of symmetric and asymmetric JLFETs is obtained using the 2D potential model shown in figure 2 by determining the gate voltage for which minimum channel potential along source to drain direction at a particular depth of the silicon channel along the top to bottom gate direction becomes zero. DIBL of JLFETs can be defined as the lowering in the threshold voltage due to the increase in the drain voltage. In this work DIBL is also calculated by varying V_{ds} from 0.1V to 1V. Figure 5 and 6 exhibits the variation of TVRO and DIBL with the channel length of symmetric and asymmetric double gate JLFETs respectively. The asymmetric structure demonstrates smaller TVRO and less DIBL than the symmetric structure when the devices are shrunk into a deep-submicrometer regime.

In this work we have obtained a 2D channel potential model in subthreshold region for double gate JLFETs. The analytical potential model is further used to determine TVRO and DIBL of symmetric and asymmetric JLFETS so that performance comparison of subthreshold characteristics can be made between different structures of JLFET.

**References:**

[1] Wann et al, IEEE Transactions on Electron Devices, 43(10), pp. 1742-1753 (1996)

[2] Colinge, Springer, p. 340 (2008).

[3] Colinge et al, Nature Nanotechnology, 5(3), pp. 225-229 (2010).

[4] Lee el al, Solid-State Electronics, 54(2), pp. 97-103 (2010).

[5] Cerdeira et al, Solid-State Electronics, 94, pp. 91-97 (2014).

[6] Cong et al, Microelectronics Reliability, 54(6), pp. 1274–1281 (2014).

[7] Jazaeri et al, IEEE Transactions on Electron Devices, 61(10), pp. 3553 - 3557 (2014).