(Invited) Novel Selector and 3D RRAM Development for High Density Non-Volatile Memory

Tuesday, October 13, 2015: 11:00
105-B (Phoenix Convention Center)
H. Yang, C. C. Tan, W. He, M. Li, Y. Jiang (Data Storage Institute, Singapore), and Y. Yang (Data Storage Institute, Singapore)
The development of a higher density non-volatile memory with the 3D vertical resistive random access memory (VRRAM) has attracted great interest from the industries. However, VRRAM currently faces the challenges in selecting the specific cell due to a large number of leakage paths, and fabrication process difficulties. In order to eliminate the sneak path and reduce the power consumption, we have developed a novel selector based on doped chalcogenide material. This novel selector shows nearly ideal selector performances with >107 on/off ratio, 0.2 V holding voltage, 10 pA off-state leakage current, sharp on-switch slope of 7 mV/dec, <10 ns turn on speed, >109 endurance, >1.6 MA/cm2 on current density. To investigate the VRRAM fabrication process, we have developed a process flow to fabricate VRRAM and demonstrated a single level sidewall TaOx based VRRAM device. These VRRAM devices can work properly and its switching performance is independent on the thickness of the switching material. Beside the novel selector and VRRAM integration investigation, we have also proposed a transistor-based novel VRRAM (TB-RRAM) architecture. By forming the RRAM cells and transistors at different layer simultaneously, the fabrication cost related to the lithography, etch and deposition can be greatly reduced.  Furthermore, with transistor as RRAM selector, better read/write endurance and reliability is expected and it is believed to be industry friendly because of the similar architecture of 3D NAND.