Influence of Focused Electron Beam on Electrical Characterization of Advanced Mosfets

Wednesday, October 14, 2015: 16:00
Remington B (Hyatt Regency)


 The focused electron beam based inspection instruments such as Scanning Electron Microscope (SEM) have become widespread in the semiconductor manufacturing and failure analysis of scaled devices. Also, nano-probing systems with SEM guidance have become important in the failure analysis area to evaluate the localized device in the actual LSI [1]. However, electron beam leads to device degradation [2] and its damage are increasing with the scaling. As CMOS scaling is going to be sub-10nm regime [3], electron beam damages are becoming critical issue in performing electrical characterization at the contact level in integrated devices using nano-probe technique. To avoid the electron damage, the acceleration voltage should be lower. However, the lower acceleration voltage of electron beam leads to lower resolution of image created by SEM guidance.

In this work, we evaluated NMOS FinFET in SRAM cells manufactured in a 10nm CMOS process with Atomic Force Microscopy (AFM) based nano-probing system. AFM based nano-probing system has no electron beam damage because it uses topography image created by AFM instead of SEM for guidance at contact level [4]. After deprocessing the samples to the contact level, we irradiated electron beams to samples to investigate a dependency of the device characteristics on electron beam acceleration voltage. Compared to a non-exposed reference transistor, the exposure of electron beam on the target transistor lead to significant changes on device characteristics such as saturation current (IDS), sub-threshold voltage (VTH) and sub-threshold swing (S). This might be due to trapped charges in the gate oxide and interface state [5]. Our studies show that it is critical to avoid electron beam exposure before electrical device characterizations are carried out at the contact level using nano-probe system since electron beam induced device parameter changes are not negligible in the failure analysis of sub-10nm devices.


[1] S. Ikeda, Y. Yoshida, K. Ishibashi, Y. Mitsui, Electron Devices, IEEE Transactions on, 50 (2003) 1270-1276.

[2] K. Nakamae, H. Fujioka, K. Ura, Journal of Applied Physics, 52 (1981) 1306-1308.

[3] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano,  Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, IEEE2005, pp. 721-724.

[4] R. Mulder, S. Subramanian, T. Chrastecky,  INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, ASM International; 2006, pp. 503.

[5] S. Shabde, A. Bhattacharyya, R.S. Kao, R.S. Muller, Solid-state electronics, 31 (1988) 1603-1610.